C6416 datasheet(50/134 Pages) TI1

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SMJ320C6414, SMJ320C6415, SMJ320C6416

FIXEDPOINT DIGITAL SIGNAL PROCESSORS

SGUS050A − JANUARY 2004 − REVISED MARCH 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

Terminal Functions (Continued)

SIGNAL

TYPE†

IPD/

‡

DESCRIPTION

NAME

NO.

TYPE†

IPD/

IPU‡

DESCRIPTION

EMIFB (16-bit) − DATA||k

BED15

BED14

J10

BED13

BED12

BED11

H10

BED10

BED9

BED8

I/O/Z

IPU

EMIFB external data

BED7

I/O/Z

IPU

EMIFB external data

BED6

BED5

G10

BED4

J11

BED3

BED2

BED1

H11

BED0

F10

MULTICHANNEL BUFFERED SERIAL PORT 2 (McBSP2)

MCBSP2_EN

AB4

IPD

McBSP2 enable pin. This pin works in conjunction with the PCI_EN pin to enable/disable other

peripherals (for more details, see the Device Configurations section of this data sheet).

CLKS2/GP8§

I/O/Z

IPD

McBSP2 external clock source (CLKS2) [input only] [default] or this pin can also be

programmed as a GPIO 8 pin (I/O/Z).

CLKR2

I/O/Z

IPD

McBSP2 receive clock. When McBSP2 is disabled (PCI_EN = 1 and MCBSP2_EN pin = 0),

this pin is tied-off.

CLKX2/

XSP_CLK§

I/O/Z

IPD

McBSP2 transmit clock (I/O/Z) [default] or PCI serial interface clock (O).

DR2/XSP_DI§

IPU

McBSP2 receive data (I) [default] or PCI serial interface data in (I). In PCI mode, this pin is

connected to the output data pin of the serial PROM.

DX2/XSP_DO§

O/Z

IPU

McBSP2 transmit data (O/Z) [default] or PCI serial interface data out (O). In PCI mode, this pin

is connected to the input data pin of the serial PROM.

FSR2

I/O/Z

IPD

McBSP2 receive frame sync. When McBSP2 is disabled (PCI_EN = 1 and MCBSP2_EN pin

= 0), this pin is tied-off.

FSX2

I/O/Z

IPD

McBSP2 transmit frame sync. When McBSP2 is disabled (PCI_EN = 1 and MCBSP2_EN pin

= 0), this pin is tied-off.

† I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground

‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite

supply rail, a 1-k

Ω resistor should be used.)

§ For the C6415 and C6416 devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.

The C6414 device does not support the PCI or UTOPIA peripherals; therefore, these MUXed peripheral pins except CLKS2/GP8 are standalone

peripheral functions for this device.

|| These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signal

whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of

discussion, the prefix “A” or “B” may be omitted from the signal name.

kTo maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.

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