C6416 datasheet(80/134 Pages) TI1

80 / 134 page

SMJ320C6414, SMJ320C6415, SMJ320C6416

FIXEDPOINT DIGITAL SIGNAL PROCESSORS

SGUS050A − JANUARY 2004 − REVISED MARCH 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

INPUT AND OUTPUT CLOCKS

timing requirements for CLKIN†‡§ (see Figure 16)

NO.

PLL MODE x12

PLL MODE x6

x1 (BYPASS)

UNIT

NO.

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

tc(CLKIN)

Cycle time, CLKIN

33.3

13.3

33.3

13.3*

33.3

tw(CLKINH) Pulse duration, CLKIN high

0.4C*

0.45C*

tw(CLKINL)

Pulse duration, CLKIN low

0.4C*

0.45C*

tt(CLKIN)

Transition time, CLKIN

*This parameter is not production tested.

† The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.

‡ For more details on the PLL multiplier factors (x6, x12), see the Clock PLL section of this data sheet.

§ C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.

CLKIN

Figure 16. CLKIN Timing

C6416 Datasheet(PDF) 80 Page - Texas Instruments

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