W25Q128FVCIP datasheet(37/97 Pages) WINBOND

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W25Q128FV

Publication Release Date: October 01, 2012

- 36 -

Revision D

8.2.8 Fast Read Dual Output (3Bh)

The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction except

that data is output on two pins; IO0 and IO1. This allows data to be transferred at twice the rate of standard

SPI devices. The Fast Read Dual Output instruction is ideal for quickly downloading code from Flash to

RAM upon power-up or for applications that cache code-segments to RAM for execution.

Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the highest

possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight

“dummy” clocks after the 24-bit address as shown in Figure 18. The dummy clocks allow the device's

internal circuits additional time for setting up the initial address. The input data during the dummy clocks is

“don’t care”. However, the IO0 pin should be high-impedance prior to the falling edge of the first data out

clock.

/CS

CLK

(IO

Mode 0

Mode 3

Instruction (3Bh)

High Impedance

24-Bit Address

/CS

CLK

(IO

Dummy Clocks

High Impedance

0 switches from

Input to Output

Data Out 1

* Data Out 2

* Data Out 3

* Data Out 4

= MSB

Figure 18. Fast Read Dual Output Instruction (SPI Mode only)

W25Q128FVCIP Datasheet(PDF) 37 Page - Winbond