CP3SP33SMSSLASHNOPB datasheet(107/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

WKCL The Wake-Up Clear bits are used to selectively clear bits in WKRPNDn and WKFPNDn.

0 – Writing 0 has no effect.

1 – Writing 1 clears the corresponding bit position in WKRPNDn and WKFPNDn.

17.1.4 Rising Edge Enable Register n (WKRENn)

The WKRENn registers are 32-bit, read/write registers that enable a wake-up event when a rising edge is

detected on the corresponding MIWU input. Bits 31:0 of WKREN1 correspond to MIWU inputs 31:0 Bits

31:0 of WKREN2 correspond to MIWU inputs 63:32. The WKRENn registers are cleared at reset. The

WKREN

The Wake-Up Rising Edge Enable bits enable a wake-up event when a rising edge

occurs on the corresponding MIWU input.

0 – No wake-up event enabled.

1 – Wake-up event enabled.

17.1.5 Falling Edge Enable Register n (WKFENn)

The WKFENn registers are 32-bit, read/write registers that enable a wake-up event when a falling edge is

detected on the corresponding MIWU input. Bits 31:0 of WKFEN1 correspond to MIWU inputs 31:0 Bits

31:0 of WKFEN2 correspond to MIWU inputs 63:32. The WKFENn registers are cleared at reset. The

WKFEN

The Wake-Up Falling Edge Enable bits enable a wake-up event when a falling edge occurs

on the corresponding MIWU input.

0 – No wake-up event enabled.

1 – Wake-up event enabled.

17.1.6 Rising Edge Interrupt Enable Register n (WKRIENn)

The WKRIENn registers are 32-bit, read/write registers that enable an interrupt when a rising edge is

detected on the corresponding MIWU input. Bits 31:0 of WKRIEN1 correspond to MIWU inputs 31:0 Bits

31:0 of WKRIEN2 correspond to MIWU inputs 63:32. The WKRIENn registers are cleared at reset. The

WKRIEN

WKRIEN The Rising Edge Interrupt Enable bits enable an interrupt when a rising edge occurs on the

corresponding MIWU input.

0 – No interrupt enabled.

1 – Interrupt enabled.

17.1.7 Falling Edge Interrupt Enable Register n (WKFIENn)

The WKFIENn registers are 32-bit registers, read/write that enable an interrupt when a falling edge is

detected on the corresponding MIWU input. Bits 31:0 of WKFIEN1 correspond to MIWU inputs 31:0 Bits

31:0 of WKFIEN2 correspond to MIWU inputs 63:32. The WKFIENn registers are cleared at reset. The

Multi-Input Wake-Up

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