H5GQ2H24AFR-R0C datasheet(126/172 Pages) HYNIX

126 / 172 page

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.2 /Nov. 2011

126

H5GQ2H24AFR

Notes:

1. Measurement procedures for each parameter must follow standard procedures defined in the current JEDEC JESD‐51 standard.

2. Theta_JA and Theta_JB must be measured with the high effective thermal conductivity test board defined in JESD51‐7.

3. Airflow information must be documented for Theta_JA.

4. Theta_JA should only be used for comparing the thermal performance of single package and not for system related junction

temperature prediction.

5. Theta_JB and Theta_JC are derived through a package thermal simulation.

6. Values are guaranteed by design but not tested in production.

Notes : DRAM Component Operating Temperature Range

Symbol

Parameter

Rating

Units

Notes

TOPER

Normal Operating Temperature Range

0 to 85

1,2

Notes:

1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measurement condi‐

tions, please refer to the JEDEC document JESD51‐2.

2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation,

the DRAM case temperature must be maintained between 0 ‐ 85oC under all operating conditions.

H5GQ2H24AFR-R0C Datasheet(PDF) 126 Page - Hynix Semiconductor