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H5GQ2H24AFR-R0C Datasheet(PDF) 140 Page - Hynix Semiconductor

Part # H5GQ2H24AFR-R0C
Description  2Gb (64Mx32) GDDR5 SGRAM
PDF  172 Pages
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

H5GQ2H24AFR-R0C Datasheet(HTML) 140 Page - Hynix Semiconductor

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.2 /Nov. 2011
140
H5GQ2H24AFR
PARAMETER a, b
SYMBOL
6.0Gbps
UNIT
NOTES
MIN
MAX
NOP/DESELECT commands required upon power-down and
self refresh entry
tCPDED
4
-
tCK
Power down exit time
tXPN
17
-
tCK
Miscellaneous Timings
MODE REGISTER SET command period
tMRD
4
-
ns
PLL enabled to PLL lock delay
tLK
5000
-
tCK
PLL standby time
tSTDBTY
TBD
-
us
ax
Required time for duty cycle corrector (DCC)
tDCC
1300
-
tCK
DVS voltage stabilization time
tVS
TBD
-
us
REFRESH to calibration update complete delay
tKO
-
40
ns
Active termination setup time
tATS
10
-
ns
Active termination hold time
tATH
10
-
ns
READ to data out delay in address training mode
tADR
0.5*tCK+0
0.5*tCK+
10
tCK
q
Address training exit to DQ in ODT state delay
tADZ
-
0.5*tCK+
10
ns
Vendor ID on
tWRIDON
-
11
ns
Venodr ID off
tWRIDOFF
-
11
ns
enable delay
tTSEN
10
-
us
Table 44. AC Timings (@1.5V)



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