H5GQ2H24AFR-R0C datasheet(163/172 Pages) HYNIX

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

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Rev. 1.2 /Nov. 2011

163

H5GQ2H24AFR

7.4. MIRROR FUNCTION (MF) ENABLE and x16 MODE ENABLE

The GDDR5 SGRAM provides a mirror function (MF) pin to change the physical location of the command,

address, data, and WCK pins assisting in routing devices back to back. The MF ball should be tied directly

to VSSQ or VDDQ depending on the control line orientation Desired. But, in case of BST(Boundary Scan

Test), it cannot be tied directly to VDDQ or VSSQ

The GDDR5 SGRAM can operate in a x32 mode or a x16 mode to allow a clamshell configuration with a

point to point connection on the high speed data signal. The disabled pins in x16 mode should all be in a

Hi‐Z state, non‐terminating.

The x16 mode is detected at power up on the pin at location C‐13 which is EDC1 when configured to MF=0

and EDC2 when configured to MF=1. For x16 mode this pin is tied to VSSQ; the pin is part of the two bytes

that are disabled in this mode and therefore not needed for EDC functionality. For x32 mode this pin is

active and always terminated to VDDQ in the system or by the controller. The configuration is set with

RESET# going High. Once the configuration has been set, it cannot be changed during normal operation.

Usually the configuration is fixed in the system. Details of the x16 mode detection are depicted in Figure .

A comparison of x32 mode and x16 mode systems is shown in Figure .

H5GQ2H24AFR-R0C Datasheet(PDF) 163 Page - Hynix Semiconductor