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H5GQ2H24AFR-R0C Datasheet(PDF) 166 Page - Hynix Semiconductor |
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H5GQ2H24AFR-R0C Datasheet(HTML) 166 Page - Hynix Semiconductor |
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166 / 172 page ![]() This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.2 /Nov. 2011 166 H5GQ2H24AFR Figure 86. Example Channel Topologies For flexibility of PCB routing GDDR5 SGRAM devices, the ball‐out includes definition of both MF=0 and MF=1. The following simple block diagrams in Figure 87 demonstrate some of the flexibility of PCB rout‐ ing. (P2P) 32 DQ (P2P) 32 DQ (P22P) ADD/CMD 16 DQ (P2P) (P22P) ADD/CMD 16 DQ 64bit channel 32 DQ 32bit channel (P2P) ADD/CMD (P2P) (P2P) |
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