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DSPIC33EP128GS708 Datasheet(PDF) 354 Page - Microchip Technology

Part # DSPIC33EP128GS708
Description  16-Bit Digital Signal Controllers for Digital Power Applications with Interconnected High-Speed PWM, ADC, PGA and Comparators
PDF  484 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

DSPIC33EP128GS708 Datasheet(HTML) 354 Page - Microchip Technology

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dsPIC33EPXXXGS70X/80X FAMILY
DS70005258C-page 354
 2016-2018 Microchip Technology Inc.
FNOSC<2:0>
Oscillator Selection bits
111 = Fast RC Oscillator with Divide-by-N (FRCDIVN)
110 = Fast RC Oscillator with Divide-by-16
101 = Low-Power RC Oscillator (LPRC)
100 = Reserved; do not use
011 = Primary Oscillator with PLL module (XT+PLL, HS+PLL, EC+PLL)
010 = Primary Oscillator (XT, HS, EC)
001 = Fast RC Oscillator with Divide-by-N with PLL module (FRCPLL)
000 = Fast RC Oscillator (FRC)
FCKSM<1:0>
Clock Switching Mode bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
IOL1WAY
Peripheral Pin Select Configuration bit
1 = Allows only one reconfiguration
0 = Allows multiple reconfigurations
OSCIOFNC
OSC2 Pin Function bit (except in XT and HS modes)
1 = OSC2 is the clock output
0 = OSC2 is a general purpose digital I/O pin
POSCMD<1:0>
Primary Oscillator Mode Select bits
11 = Primary Oscillator is disabled
10 = HS Crystal Oscillator mode
01 = XT Crystal Oscillator mode
00 = EC (External Clock) mode
WDTEN<1:0>
Watchdog Timer Enable bits
11 = Watchdog Timer is always enabled (LPRC oscillator cannot be disabled; clearing the
SWDTEN bit in the RCON register will have no effect)
10 = Watchdog Timer is enabled/disabled by user software (LPRC can be disabled by
clearing the SWDTEN bit in the RCON register)
01 = Watchdog Timer is enabled only while device is active and is disabled while in Sleep
mode; software control is disabled in this mode
00 = Watchdog Timer and SWDTEN bit are disabled
WINDIS
Watchdog Timer Window Enable bit
1 = Watchdog Timer is in Non-Window mode
0 = Watchdog Timer is in Window mode
PLLKEN
PLL Lock Enable bit
1 = PLL lock is enabled
0 = PLL lock is disabled
WDTPRE
Watchdog Timer Prescaler bit
1 = 1:128
0 = 1:32
WDTPOST<3:0>
Watchdog Timer Postscaler bits
1111 = 1:32,768
1110 = 1:16,384
•
•
•
0001 = 1:2
0000 = 1:1
TABLE 27-2:
CONFIGURATION BITS DESCRIPTION (CONTINUED)
Bit Field
Description
Note 1:
The Boot Segment must be present to use the Alternate Interrupt Vector Table.



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