DSPIC33EP128GS708 datasheet(352/484 Pages) MICROCHIP

352 / 484 page

TABLE 27-1:

CONFIGURATION REGISTER MAP(3)

Name

Address

Device

Memory

Size

(Kbytes)

Bits 23-16

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

FSEC

00AF80

—

AIVTDIS

—

CSS<2:0>

CWRP

GSS<1:0>

GWRP

—

BSEN

BSS<1:0>

BWRP

015780

128

FBSLIM

00AF90

—

BSLIM<12:0>

015790

128

FSIGN

00AF90

—

Reserved(2)

—

015794

128

FOSCSEL

00AF98

—

IESO

—

—FNOSC<2:0>

015798

128

FOSC

00AF9C

—

PLLKEN

FCKSM<1:0>

IOL1WAY

—

OSCIOFNC

POSCMD<1:0>

01579C

128

FWDT

00AFA0

—

WDTWIN<1:0>

WINDIS

WDTEN<1:0>

WDTPRE

WDTPOST<3:0>

0157A0

128

FPOR

00AFA4

—

Reserved(1)

0157A4

128

FICD

00AFA8

—BTSWP

—

Reserved(1)

—JTAGEN

—

—ICS<1:0>

0157A8

128

FDEVOPT 00AFAC

—

—DBCC

—

ALTI2C2 ALTI2C1 Reserved(1)

—PWMLOCK

0157AC

128

FALTREG 00AFB0

—

CTXT4<2:0>

—CTXT3<3:0>

—

CTXT2 <2:0>

—

CTXT1 <2:0>

0157B0

128

FBTSEQ 00AFFC

IBSEQ<11:0>

BSEQ<11:0>

0157FC

128

FBOOT(4) 801000

—

BTMODE<1:0>

Note 1:

These bits are reserved and must be programmed as ‘1’.

This bit is reserved and must be programmed as ‘0’.

When operating in Dual Partition Flash mode, each partition will have dedicated Configuration registers. On a device Reset, the configuration values of the Active Partition are read at start-up, but during a soft

swap condition, the configuration settings of the newly Active Partition are ignored.

FBOOT resides in configuration memory space.

DSPIC33EP128GS708 Datasheet(PDF) 352 Page - Microchip Technology

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