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DSPIC33EP128GS708 Datasheet(PDF) 353 Page - Microchip Technology |
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DSPIC33EP128GS708 Datasheet(HTML) 353 Page - Microchip Technology |
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353 / 484 page  2016-2018 Microchip Technology Inc. DS70005258C-page 353 dsPIC33EPXXXGS70X/80X FAMILY TABLE 27-2: CONFIGURATION BITS DESCRIPTION Bit Field Description BSS<1:0> Boot Segment Code-Protect Level bits 11 = Boot Segment is not code-protected other than BWRP 10 = Standard security 0x = High security BSEN Boot Segment Control bit 1 = No Boot Segment is enabled 0 = Boot Segment size is determined by the BSLIM<12:0> bits BWRP Boot Segment Write-Protect bit 1 = Boot Segment can be written 0 = Boot Segment is write-protected BSLIM<12:0> Boot Segment Flash Page Address Limit bits Contains the last active Boot Segment page. The value to be programmed is the inverted page address, such that programming additional ‘0’s can only increase the Boot Segment size (i.e., 0x1FFD = 2 Pages or 1024 IW). GSS<1:0> General Segment Code-Protect Level bits 11 = User program memory is not code-protected 10 = Standard security 0x = High security GWRP General Segment Write-Protect bit 1 = User program memory is not write-protected 0 = User program memory is write-protected CWRP Configuration Segment Write-Protect bit 1 = Configuration data is not write-protected 0 = Configuration data is write-protected CSS<2:0> Configuration Segment Code-Protect Level bits 111 = Configuration data is not code-protected 110 = Standard security 10x = Enhanced security 0xx = High security BTSWP BOOTSWP Instruction Enable/Disable bit 1 = BOOTSWP instruction is disabled 0 = BOOTSWP instruction is enabled BSEQ<11:0> Boot Sequence Number bits (Dual Partition modes only) Relative value defining which partition will be active after device Reset; the partition containing a lower boot number will be active. IBSEQ<11:0> Inverse Boot Sequence Number bits (Dual Partition modes only) The one’s complement of BSEQ<11:0>; must be calculated by the user and written for device programming. If BSEQx and IBSEQx are not complements of each other, the Boot Sequence Number is considered to be invalid. AIVTDIS(1) Alternate Interrupt Vector Table bit 1 = Alternate Interrupt Vector Table is disabled 0 = Alternate Interrupt Vector Table is enabled if INTCON2<8> = 1 IESO Two-Speed Oscillator Start-up Enable bit 1 = Starts up device with FRC, then automatically switches to the user-selected oscillator source when ready 0 = Starts up device with the user-selected oscillator source PWMLOCK PWMx Lock Enable bit 1 = Certain PWMx registers may only be written after a key sequence 0 = PWMx registers may be written without a key sequence Note 1: The Boot Segment must be present to use the Alternate Interrupt Vector Table. |
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