HC705CT4GRSSLASHD datasheet(71/152 Pages) NXP

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Synchronous Serial Interface (SSI)

Signal Format

MC68HC705CT4 — Rev. 2.0

General Release Specification

MOTOROLA

Synchronous Serial Interface (SSI)

9.3 Signal Format

The SSI is comprised of two main input/output (I/O) signals that interface

with port D serial clock and serial data.

9.3.1 Serial Clock (SCK)

When SE = 0, this pin is a port D bit 5 pin, which follows the port D DDR

assignment.

In master mode (MSTR = 1), the serial clock (SCK) pin is an output with

four selectable frequencies. This pin will be high (CPOL = 1) or low

(CPOL = 0) between transmissions.

In slave mode (MSTR = 0), the SCK pin is an input and the clock must

be supplied by an external master with a maximum frequency of f

OP/2.

There is no minimum SCK frequency. This pin should be driven high

(CPOL = 1) or low (CPOL = 0) between transmissions by the external

master and must be stable before the SSI is first enabled (SE = 1).

Data is always captured at the serial data in/out (SDIO) pin on the rising

edge of SCK.

Data is always shifted out and presented at the serial data in/out (SDIO)

pin on the falling edge of SCK.

9.3.2 Serial Data In/Out (SDIO)

Prior to enabling the SSI (SE = 0), the serial data in/out (SDIO) pin is a

port D bit 4 pin, which follows the port D DDR assignment. When the SSI

is enabled (SE = 1) the SDIO pin becomes a high-impedance input pin

if the T/R bit is low or it idles high if the T/R bit is high.

The data can be sent or received in either MSB first format (LSBF = 0)

or LSB first format (LSBF = 1).

If (CPOL = 1), the first falling edge of SCK will shift the first data bit out

to the SDIO pin. Subsequent falling edges of SCK will shift the remaining

data bits out.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705CT4GRS/D Datasheet(PDF) 71 Page - NXP Semiconductors