HC705CT4GRSSLASHD datasheet(108/152 Pages) NXP

108 / 152 page

EPROM

General Release Specification

MC68HC705CT4 — Rev. 2.0

108

EPROM

MOTOROLA

15.4 Bootloader Mode

Bootloader mode is entered upon the rising edge of RESET if the IRQ is

at VTST and the PB1 pin is at logic 1. The bootloader code resides in the

ROM from $1F01 to $1FEF. This program handles copying of user code

from an external EPROM into the on-chip EPROM. The bootload

function does not have to be done from an external EPROM, but it may

be done from a host.

The user code must be a one-to-one correspondence with the internal

EPROM addresses.

NOTE:

The MCU designer must disable the COP hardware in bootloader mode.

15.4.1 Bootloader Functions

Three pins are used to select various bootloader functions: PB0, PB3,

and PB4. PB0 is normally a SYNC pin, which is used to synchronize the

MCU to an off-chip source driving EPROM data into the MCU. If an

external EPROM is used, this pin must be connected to VSS. PB4 and

PB3 are used to select a programming mode. Two other pins, PC2 and

PC3, are used to drive the PROG LED and the VERF LED, respectively.

The programming modes, along with GATE and DRAIN stress, are

shown in Table 15-1.

The bootloader uses an external 12-bit counter to address the memory

device containing the code to be copied. This counter requires a clock

and a reset function. The 12-bit counter can address up to 4 Kbytes of

Table 15-1. Bootloader Functions

PB0

PB4

PB3

Mode

SYNC

Program/Verify

SYNC

Verify Only

SYNC

Dump EPROM

Gate Stress

Drain Stress

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705CT4GRS/D Datasheet(PDF) 108 Page - NXP Semiconductors

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