STC12LE5616AD datasheet(145/377 Pages) STC

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6.6 Response Time

The INT0 and INT1 levels are inverted and latched into the interrupt flags IE0 and IE1 at rising edge of every

syetem clock cycle.

The Timer 0 and Timer 1 flags, TF0 and TF1, are set after which the timers overflow. The values are then polled

by the circuitry at rising edge of the next system clock cycle.

If a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the

requested service routine will be the next instruction to be executed. The call itself takes six system clock cycles.

Thus, a minimum of seven complete system clock cycles elapse between activation of an external interrupt

request and the beginning of execution of the first instruction of the service routine.

A longer response time would result if the request is blocked by one of the four previously listed conditions. If an

interrupt of equal or higher priority level is already in progress, the additional wait time obviously depends on the

nature of the other interrupt’s service routine. If the instruction in progress is not in its final cycle, the additional

wait time cannot be more than 3 cycles, since the longest instructions (LCALL) are only 6 cycles long, and if the

instruction in progress is RETI or an access to IE or IP, the additional wait time cannot be more than 5 cycles (a

maximum of one more cycle to complete the instruction in progress, plus 6 cycles to complete the next instruction

if the instruction is LCALL).

Thus, in a single-interrupt system, the response time is always more than 7 cycles and less than 12 cycles.

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