STC12LE5616AD datasheet(141/377 Pages) STC

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Source

Vector Address

External Interrupt 0

0003H

Timer 0

000BH

External Interrupt 1

0013H

Timer 1

001BH

UART

0023H

ADC/SPI

002BH

PCA/LVD

0033H

Execution proceeds from that location until the RETI instruction is encountered. The RETI instruction informs

the processor that this interrupt routine is no longer in progress, then pops the top two bytes from the stack and

reloads the Program Counter. Execution of the interrupted program continues from where it left off.

Note that a simple RET instruction would also have returned execution to the interrupted program, but it would

have left the interrupt control system thinking an interrupt was still in progress.

6.5 External Interrupts

The external sources can be programmed to be level-activated or transition-activated by clearing or setting bit IT1

or IT0 in Register TCON. If ITx = 0, external interrupt x is triggered by a detected low at the INTx pin. If ITx=1,

external interrupt x is edge-triggered. In this mode if successive samples of the INTx pin show a high in one cycle

and a low in the next cycle, interrupt request flag IEx in TCON is set. Flag bit IEx then requests the interrupt.

Since the external interrupt pins are sampled once each machine cycle, an input high or low should hold for at

least 12 system clocks to ensure sampling. If the external interrupt is transition-activated, the external source has

to hold the request pin high for at least one machine cycle, and then hold it low for at least one machine cycle to

ensure that the transition is seen so that interrupt request flag IEx will be set. IEx will be automatically cleared by

the CPU when the service routine is called.

If the external interrupt is level-activated, the external source has to hold the request active until the requested

interrupt is actually generated. Then it has to deactivate the request before the interrupt service routine is

completed, or else another interrupt will be generated.

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