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STC12LE5616AD Datasheet(PDF) 138 Page - STCmicro Technology Co,.Ltd |
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STC12LE5616AD Datasheet(HTML) 138 Page - STCmicro Technology Co,.Ltd |
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138 / 377 page ![]() 9. Interrupt register related with Power down wake-up: WAKE_CLKO (Non bit-Addressable) SFR name Address bit B7 B6 B5 B4 B3 B2 B1 B0 WAKE_CLKO 8FH name PCAWAKEUP RXD_PIN_IE T1_PIN_IE T0_PIN_IE - - T1CKLO T0CKLO PCAWAKEUP: When set and the associated-PCA interrupt control registers is configured correctly, the CEXn pin of PCA function is enabled to wake up MCU from power-down state. RXD_PIN_IE: When set and the associated-UART interrupt control registers is configured correctly, the RXD pin (P3.0) is enabled to wake up MCU from power-down state. T1_PIN_IE : When set and the associated-Timer1 interrupt control registers is configured correctly, the T1 pin (P3.5) is enabled to wake up MCU from power-down state. T0_PIN_IE : When set and the associated-Timer0 interrupt control registers is configured correctly, the T1 pin (P3.4) is enabled to wake up MCU from power-down state. T1CKLO : When set, P3.5 is enabled to be the clock output of Timer 1. The clock rate is Timer 1overflow rate divided by 2. T0CKLO : When set, P3.4 is enabled to be the clock output of Timer 0. The clock rate is Timer 0overflow rate divided by 2. 8. Register related with SPI interrupt : SPSTAT SPI State register: SPSTAT (Non bit-addressable) SFR name Address bit B7 B6 B5 B4 B3 B2 B1 B0 SPSTAT CDH name SPIF WCOL ------ SPIF : SPI transfer completion flag. When a serial transfer finishes, the SPIF bit is set and an interrupt is generated if all the EADC_SPI (IE.6) bit, ESPI bit (AUXR.3) and the EA (IE.7) bit are set. If SS is an input and is driven low when SPI is in master mode with SSIG = 0, SPIF will also be set to signal the “mode change”.The SPIF is cleared in software by “writing 1 to this bit”. WCOL: SPI write collision flag. The WCOL bit is set if the SPI data register, SPDAT, is written during a data transfer. The WCOL flag is cleared in software by “writing 1 to this bit”. IE: Interrupt Enable Rsgister (Bit-addressable) SFR name Address bit B7 B6 B5 B4 B3 B2 B1 B0 IE A8H name EA EPCA_LVD EADC_SPI ES ET1 EX1 ET0 EX0 EA : disables all interrupts. If EA = 0,no interrupt will be acknowledged. If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. EADC_SPI : Interrupt controller of Serial Peripheral Interface (SPI) and A/D Converter (ADC). If EADC_SPI = 0, Disable the interrupt of Serial Peripheral Interface (SPI) and A/D Converter (ADC). If EADC_SPI = 1, Enable the interrupt of Serial Peripheral Interface (SPI) and A/D Converter (ADC). 138 |
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