STC12LE5616AD datasheet(134/377 Pages) STC

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4. SCON register: Serial Port 1 (UART1) Control Register (Bit-Addressable)

SFR name

Address

bit

SCON

98H

name

SM0/FE

SM1

SM2

REN

TB8

RB8

FE: Framing Error bit. The SMOD0 bit must be set to enable access to the FE bit

0: The FE bit is not cleared by valid frames but should be cleared by software.

1: This bit set by the receiver when an invalid stop bit id detected.

SM0,SM1 : Serial Port Mode Bit 0/1.

SM0

SM1

Description

Baud rate

8-bit shift register

SYSclk/12

8-bit UART

variable

9-bit UART

SYSclk/64 or SYSclk/32(SMOD=1)

9-bit UART

variable

SM2 : Enable the automatic address recognition feature in mode 2 and 3. If SM2=1, RI will not be

set unless the received 9th data bit is 1, indicating an address, and the received byte is a

Given or Broadcast address. In mode1, if SM2=1 then RI will not be set unless a valid stop

Bit was received, and the received byte is a Given or Broadcast address. In mode 0, SM2 should be 0.

REN : When set enables serial reception.

TB8 : The 9th data bit which will be transmitted in mode 2 and 3.

RB8 : In mode 2 and 3, the received 9th data bit will go into this bit.

TI : Transmit interrupt flag. Set by hardware when a byte of data has been transmitted by UART0 (after the 8th

bit in 8-bit UART Mode, or at the beginning of the STOP bit in 9-bit UART Mode). When the UART0 in-

terrupt is enabled, setting this bit causes the CPU to vector to the UART0 interrupt service routine. This bit

must be cleared manually by software.

RI : Receive interrupt flag. Set to ‘1’ by hardware when a byte of data has been received by UART0 (set at the

STOP bit sam-pling time). When the UART0 interrupt is enabled, setting this bit to ‘1’ causes the CPU to

vector to the UART0 interrupt service routine. This bit must be cleared manually by software.

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