STC12LE5616AD datasheet(133/377 Pages) STC

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3. TCON register: Timer/Counter Control Register (Bit-Addressable)

SFR name

Address

bit

TCON

88H

name TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

TF1: Timer/Counter 1 Overflow Flag. Set by hardware on Timer/Counter 1 overflow. The flag can be cleared by

software but is automatically cleared by hardware when processor vectors to the Timer 1 interrupt routine.

If TF1 = 0, No Timer 1 overflow detected.

If TF1 = 1, Timer 1 has overflowed.

TR1: Timer/Counter 1 Run Control bit. Set/cleared by software to turn Timer/Counter on/off.

If TR1 = 0, Timer 1 disabled.

If TR1 = 1, Timer 1 enabled.

TF0: Timer/Counter 0 Overflow Flag. Set by hardware on Timer/Counter 0 overflow. The flag can be cleared by

software but is automatically cleared by hardware when processor vectors to the Timer 0 interrupt routine.

If TF0 = 0, No Timer 0 overflow detected.

If TF0 = 1, Timer 0 has overflowed.

TR0: Timer/Counter 0 Run Control bit. Set/cleared by software to turn Timer/Counter on/off.

If TR0 = 0, Timer 0 disabled.

If TR0 = 1, Timer 0 enabled.

IE1: External Interrupt 1 Edge flag. Set by hardware when external interrupt edge/level defined by IT1 is

detected. The flag can be cleared by software but is automatically cleared when the external interrupt 1

service routine has been processed.

IT1: External Intenupt 1 Type Select bit. Set/cleared by software to specify falling edge/low level triggered ex-

ternal interrupt 1.

If IT1 = 0, INT1 is low level triggered.

If IT1 = 1, INT1 is edge triggered.

IE0: External Interrupt 0 Edge flag. Set by hardware when external interrupt edge/level defined by IT0 is

detected. The flag can be cleared by software but is automatically cleared when the external interrupt 0

service routine has been processed.

IT0: External Intenupt 0 Type Select bit. Set/cleared by software to specify falling edge/low level triggered ex-

ternal interrupt 0.

If IT0 = 0, INT0 is low level triggered.

If IT0 = 1, INT0 is edge triggered.

133

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