S75WS256NDFBAWMB datasheet(108/216 Pages) SPANSION

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S75WS256Nxx Based MCPs

S75WS-N-00_00_A0 February 17, 2005

Data

Sheet

18.8.1

Dynamic Protection Bit (DYB)

A volatile protection bit is assigned for each sector. After power-up or hardware reset, the con-

tents of all DYBs is cleared erased to 1. In other words, the DYB powers-up in an unprotected

state. Each DYB is individually modifiable through the DYB Write Command.

The Protection State for each sector is determined by the DYB related to that sector. The DYBs

control whether or not the sector is protected or unprotected. By issuing the DYB Write com-

mand sequences, the DYBs will be set (programmed to 0) or cleared (erased to 1), thus placing

each sector in the protected or unprotected state. These are the so-called Dynamic Locked or

Unlocked states. They are called dynamic states because it is very easy to switch back and forth

between the protected and unprotected conditions. This allows software to easily protect sectors

against inadvertent changes yet does not prevent the easy removal of protection when changes

are needed. The DYBs maybe set or cleared as often as needed.

18.9 Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby

mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the

high impedance state, independent of the OE# input.

The device enters the CMOS standby mode when the CE# and RESET# inputs are both held at

VCC. The device requires standard access time (tCE) for read access, before it is ready to read

data.

If the device is deselected during erasure or programming, the device draws active current until

the operation is completed.

ICC3 in the DC Characteristics section represents the standby current specification.

18.10 Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. While in asynchronous

mode, the device automatically enables this mode when addresses remain stable for tACC + 20

ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Stan-

dard address access timings provide new data when addresses are changed. While in sleep mode,

output data is latched and always available to the system. While in synchronous mode, the Auto-

matic Sleep Mode is disabled. Note that a new burst operation is required to provide new data.

ICC6 in the DC Characteristics section represents the automatic sleep mode current specification.

18.11 RESET#: Hardware Reset Input

The RESET# input provides a hardware method of resetting the device to reading array data.

When RESET# is driven low for at least a period of tRP, the device immediately terminates any

operation in progress, tristates all outputs, resets the configuration register, and ignores all read/

write commands for the duration of the RESET# pulse. The device also resets the internal state

machine to reading array data. The operation that was interrupted should be reinitiated once the

device is ready to accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS, the device

draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS, the standby cur-

rent will be greater.

RESET# may be tied to the system reset circuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up firmware from the Flash memory.

If RESET# is asserted tRP operation, the device requires a time of tRH + tRP before the device is

ready to read data again. If RESET# is asserted when a program or erase operation is not exe-

cuting, the reset operation is completed within a time of tRP (not during Embedded Algorithms).

The system can read data tRH after RESET# returns to VIH.

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