S75WS256NDFBAWMB datasheet(119/216 Pages) SPANSION

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February 17, 2005 S75WS-N-00_00_A0

S75WS256Nxx Based MCPs

117

Data

Sheet

19.8.1

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to primarily program to the device faster than using

the standard word program command sequence. The unlock bypass command sequence is initi-

ated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock

bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock by-

pass program command sequence is all that is required to program in this mode. The first cycle

in this sequence contains the unlock bypass program command, A0h; the second cycle contains

the program address and data. Additional data is programmed in the same manner. This mode

dispenses with the initial two unlock cycles required in the standard program command sequence,

resulting in faster total programming time.

During the unlock bypass mode, only the Unlock Bypass Program command is valid. To exit the

unlock bypass mode, the system must issue the two-cycle unlock bypass reset command se-

quence. The first cycle must contain the data 90h. The second cycle need only contain the data

00h. The device then returns to the read mode.

19.9 Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing

two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then

followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The

device does not require the system to preprogram prior to erase. The Embedded Erase algorithm

automatically preprograms and verifies the entire memory for an all zero data pattern prior to

electrical erase. The system is not required to provide any controls or timings during these oper-

ations. The Command Definitions table shows the address and data requirements for the chip

erase command sequence.

When the Embedded Erase algorithm is complete, the device returns to the read mode and ad-

dresses are no longer latched. The system can determine the status of the erase operation by

using DQ7 or DQ6/DQ2. Refer to the Write Operation Status section for information on these sta-

tus bits.

Any commands written during the chip erase operation are ignored. However, note that a hard-

ware reset immediately terminates the erase operation. If that occurs, the chip erase command

sequence should be reinitiated once the device has returned to reading array data, to ensure data

integrity.

Figure 20.4 illustrates the algorithm for the erase operation. Refer to the Erase/Program Opera-

tions table in the AC Characteristics section for parameters and timing diagrams.

19.10 Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writ-

ing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written,

and are then followed by the address of the sector to be erased, and the sector erase command.

The Command Definitions table shows the address and data requirements for the sector erase

command sequence.

The device does not require the system to preprogram prior to erase. The Embedded Erase algo-

rithm automatically programs and verifies the entire memory for an all zero data pattern prior to

electrical erase. The system is not required to provide any controls or timings during these

operations.

After the command sequence is written, a sector erase time-out of no less than 50 µs occurs.

During the time-out period, additional sector addresses and sector erase commands may be writ-

ten. Loading the sector erase buffer may be done in any sequence, and the number of sectors

may be from one sector to all sectors. The time between these additional cycles must be less than

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