VNF9Q20F datasheet(61/109 Pages) STMICROELECTRONICS

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Figure 28. Status registers

Preliminary

diagnosis

Error or

dedicated bit

(0..7)

End

no errors detected

No errors

Yes

Check Global status byte

(GSB)

Preliminary diagnosis does not distinguish

which device channel reports error

Additional error flags from other status

registers are provided

From GSB + from other

Status register

Communication

error

Chip reset

Overtemperature

Power limitation

Overload / VDS

Frame

temperature

pre-warning

Channel

latch OFF

Open-load in OFF

state / short to VCC

Undervoltage VCCUV

in register OUTSRx

5.3.1

Status register

Table 41. Status register

Address

Name

Access

Description

20h to 23h

OUTSRx

Read/Clear

Outputs status Register (see register map for detailed description).

28h to 2Bh

ADCxSR

Read

Digital current sense registers.

31h

ADC9SR

Read

Digital case temperature sensor voltage sense register.

5.4

Overload (VDS high voltage, overload - OVL)

Detection of potential overload condition can be performed monitoring the digital current sense registers

(ADCxSR). On top of that, the voltage drop on the PowerMOS output stage of each channel is monitored:

•

If VDS (voltage across PowerMOS output stage) exceeds the threshold defined by the parameter

(VCC

‑ VDSH_TH), an overload condition is detected. In this case, the corresponding real time bit VDSHSRx

of the OUTSRx registers (addresses from 20h to 23h) is set.

•

If VDS is lower than the threshold (VCC - VDSH_TH), this bit is automatically reset.

To avoid false fault indications, it is recommended to perform this check when the channel is in a permanent on-

state condition.

5.5

Open-load on-state detection

The open-load ON-state is performed by reading the digital current sense.

VNF9Q20F

Diagnostic

DS13909 - Rev 6

page 61/109

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