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VNF9Q20F Datasheet(PDF) 41 Page - STMicroelectronics |
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VNF9Q20F Datasheet(HTML) 41 Page - STMicroelectronics |
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41 / 109 page ![]() SOCR Channel control register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R/W - R/W R Address: 0x13h Type: R/W Reset: 0 Description: Channel control register [15] Exit capacitive charging mode on channel 3 (active high). This bit is automatically reset. [14] Exit capacitive charging mode on channel 2 (active high). This bit is automatically reset. [13] Exit capacitive charging mode on channel 1 (active high). This bit is automatically reset. [12] Exit capacitive charging mode on channel 0 (active high). This bit is automatically reset. [11] SOCR bit controls output state of channel 3 1 – output enabled 0 – output disabled [10] SOCR bit controls output state of channel 2 1 – output enabled 0 – output disabled [9] SOCR bit controls output state of channel 1 1 – output enabled 0 – output disabled [8] SOCR bit controls output state of channel 0 1 – output enabled 0 – output disabled [7:6] RESERVED [5] Capacitive charging mode on channel 3 1 – enabled 0 – disabled This bit is automatically reset. [4] Capacitive charging mode on channel 2 1 – enabled 0 – disabled This bit is automatically reset. [3] Capacitive charging mode on channel 1 1 – enabled 0 – disabled This bit is automatically reset. VNF9Q20F SPI functional description DS13909 - Rev 6 page 41/109 |
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