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TMP89FS60 Datasheet(PDF) 333 Page - Toshiba Semiconductor

Part # TMP89FS60
Description  8 Bit Microcontroller
PDF  410 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMP89FS60 Datasheet(HTML) 333 Page - Toshiba Semiconductor

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TMP89FS60
RA003
10. Set FLSCR1<FLSMD> to "0y010", and then set "0xD5" on FLSCR2<CR1EN> (to disable the
execution of the command sequence).
Note 1: If the RAM loader is used in serial PROM mode, the BOOTROM disables (DI) a maskable interrupt,
and the interrupt vector area is designated as a RAM area (SYSCR3<RVCTR>="1"). Considering that
a nonmaskable interrupt may be generated unexpectedly, it is recommended that vector addresses
corresponding these interrupts (INTUNDEF, INTSWI: 0x01F8 to 0x01F9, WDT: 0x01FC to 0x01FD)
be established and that an interrupt service routine be defined inside the RAM area.
Note 2: If a certain interrupt is used in the RAM loader program, a vector address corresponding to that inter-
rupt and the interrupt service routine must be established inside the RAM area. In this case, it is rec-
ommended that a nonmaskable interrupt be handled as explained in Note 1.
Note 3: Do not set SYSCR3<RVCTR> to "0" by using the RAM loader program. If an interrupt occurs with
SYSCR3<RVCTR> set to "0", the BOOTROM area is referenced as a vector address and, therefore,
the program will not function properly.
Example: A case in which a program is transferred to RAM, the sector erase is performed on 0xE000 through 0xEFFF
in the code area, and then data of 0x3F is written to 0xE500.
main section code abs = 0x0100
; #### Set a nonmaskable interrupt vector inside the RAM area #### (step 3)
LD
HL,0x01FC
; Set INTUNDEF and INTSWI interrupt vectors
LDW
(HL),sINTSWI
LD
HL,0x01F8
; Set INTWDT interrupt vector
LDW
(HL),sINTWDT
; #### Sector erase and write process ####
LD
HL,0xF555
; Variable for command sequence
LD
DE,0xFAAA
; Variable for command sequence
; Sector erase process (step 5)
LD
C,0x00
; Set upper address
LD
IX,0xE000
; Set middle and lower addresses
CALL
sSectorErase
; Perform a sector erase (0xE000)
; Write process (step 8)
LD
C,0x00
; Set upper address
LD
IX,0xE500
; Set middle and lower addresses
LD
B,0x3F
; Data to be written
CALL
sByteProgram
; Write process (0xE500)
; #### Execute the next main program ####
:
:
; Execute the main program
J
XXXXX
; #### Program to be executed in RAM ####
sSectorErase:
CALL
sAddConv
; Address conversion process
; Sector erase pro-
cess
LD
(HL),E
; 1st Bus Write Cycle (note 1)
LD
(DE),L
; 2nd Bus Write Cycle (note 1)
LD
(HL),0x80
; 3rd Bus Write Cycle (note 1)
LD
(HL),E
; 4th Bus Write Cycle (note 1)
LD
(DE),L
; 5th Bus Write Cycle (note 1)
LD
(IX),0x30
; 6th Bus Write Cycle (note 1)
JsRAMopEnd
; Write process
sByteProgram:
CALL
sAddConv
; Convert address
LD
(HL),E
; 1st Bus Write Cycle (note 1)
LD
(DE),L
; 2nd Bus Write Cycle (note 1)
LD
(HL),0xA0
; 3rd Bus Write Cycle (note 1)
LD
(IX),B
; 4th Bus Write Cycle (note 1)
; End process
sRAMopEnd
NOP
; (note 2)
NOP
; (note 2)
NOP
; (note 2)
sLOOP1:
LD
A,(IX)
; (step 6,9)
CMP
A,(IX)
J
NZ,sLOOP1
; Loop until the read values become the same
LD
(FLSCR1),0x40
; Disable the execution of command sequence (step 10)
LD
(FLSCR2),0xD5
; Reflect the FLSCR1 setting
RET
; Return to flash memory
; Convert address (steps 4 and 7)



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