TMP89FS60 datasheet(336/410 Pages) TOSHIBA

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Page 322

21. Flash Memory

21.4 Toggle Bit (D6)

TMP89FS60

RA003

Note 3: Before jumping from the flash memory to the RAM area, RAM must be allocated to the code area by

making the appropriate SYSCR3<RAREA> setting (setting made in step 4 in the procedure described

on the previous page).

Example: Case in which a program is transferred to RAM, a sector erase is performed on 0xE000 through 0xEFFF in

the code area, and then 0x3F data is written to 0xE500.

cRAMStartAdd

equ 0x0200

; RAM start address

main section code abs = 0x1000

; Disable interrupts (step 1)

; #### Transfer the program to RAM #### (step 2)

HL,cRAMStartAdd

IX,sRAMprogStart

sRAMLOOP:

A,(IX)

; Transfer the program from sRAMprogStart to

(HL),A

; sRAMprogEnd to cRAMStartAdd.

INC

CMP

IX,sRAMprogEnd

JNZ,sRAMLOOP

; #### Set a nonmaskable interrupt vector inside the RAM area #### (step 3)

HL,0x01FC

; Set INTUNDEF and INTSWI interrupt vectors

LDW

(HL),sINTSWI - sRAMprogStart + cRAMStartAdd

HL,0x01F8

; Set INTWDT interrupt vector

LDW

(HL),sINTWDT - sRAMprogStart + cRAMStartAdd

; #### Allocate RAM to the code area. Switch the vector area to RAM #### (step 4)

(SYSCR3),0x06

; Set RAREA and RVCTR to "1"

(SYSCR4),0xD4

; Enable Code

; #### Sector erase and write process ####

HL,0xF555

; Variable for command sequence

DE,0xFAAA

; Variable for command sequence

; Sector erase process (step 5)

C,0x00

; Set upper addresses

IX,0xE000

; Set middle and lower addresses

CALL

sRAMStartAdd

; Perform a sector erase (0xE000)

; Write process (step 11)

C,0x00

; Set upper addresses

IX,0xE500

; Set middle and lower addresses

B,0x3F

; Data to be written

CALL

sByteProgram - sRAMprogStart + cRAMStartAdd

; Write process (0xE500)

; #### Execute the next main program ####

; Execute the main program

XXXXX

; #### Program to be executed in RAM ####

sRAMprogStart:

sSectorErase:

CALL

sAddConv - sRAMprogStart + cRAMStartAdd

; Address conversion process

; Sector erase process (step 7)

(HL),E

; 1st Bus Write Cycle (note 1)

(DE),L

; 2nd Bus Write Cycle (note 1)

(HL),0x80

; 3rd Bus Write Cycle (note 1)

(HL),E

; 4th Bus Write Cycle (note 1)

(DE),L

; 5th Bus Write Cycle (note 1)

(IX),0x30

; 6th Bus Write Cycle (note 1)

JsRAMopEnd

; Write process (step 13)

sByteProgram

CALL

sAddConv - sRAMprogStart + cRAMStartAdd

; Address conversion process

(HL),E

; 1st Bus Write Cycle (note 1)

(DE),L

; 2nd Bus Write Cycle (note 1)

(HL),0xA0

; 3rd Bus Write Cycle (Note 1)

(IX),B

; 4th Bus Write Cycle (note 1)

; End process

sRAMopEnd:

NOP

; (note 2)

NOP

; (note 2)

NOP

; (note 2)

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