TMP89FS60 datasheet(334/410 Pages) TOSHIBA

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Page 320

21. Flash Memory

21.4 Toggle Bit (D6)

TMP89FS60

RA003

Note 1: In using a write instruction in the xxx bus write cycle, make sure that you use a write instruction of

more than three machine cycles or arrange write instructions in such a way that they are generated at

intervals of three or more machine cycles. If a 16-bit transfer instruction is used or if write instructions

are executed at intervals of two machine cycles, the flash memory command sequence will not be

transmitted properly, and a malfunction may occur.

Note 2: If a read of the flash memory (toggle operation) is to be performed after a write instruction is gener-

ated in the xth bus write cycle, instructions must be arranged in such a way that they are generated at

intervals of three or more machine cycles; machine cycles are counted from when the last xth bus

write cycle is generated to when each instruction is generated. Three NOP instructions are normally

used. If the interval between instructions is short, the toggle bit does not operation correctly.

sAddConv:

WA,IX

SWAP

AND

C,0x10

SWAP

AND

W,0x08

C,W

XOR

C,0x08

SHRC

C,0xA0

(FLSCR1),C

; Enable the execution of command sequence. Make the

FAREA setting.

(FLSCR2),0xD5

; Reflect the FLSCR1 setting

WA,IX

TEST

C.3

Z,sAddConvEnd

W,0x80

IX,WA

sAddConvEnd:

RET

; Interrupt subrou-

tine

sINTWDT:

; Error processing

RETN

sINTSWI:

; Error processing

RETN

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