TMP89FS60 datasheet(175/410 Pages) TOSHIBA

175 / 410 page

Page 161

TMP89FS60

RA001

13.4.6.3 Register buffer configuration

(1)

Temporary buffer

The TMP89FS60 contains an 8-bit temporary buffer. When a write instruction is executed on

TA0DRAL (TA0DRBL), the data is first stored into this temporary buffer, whether the double buffer

is enabled or disabled. Subsequently, when a write instruction is executed on TA0DRAH

(TA0DRBH), the set value is stored into the double buffer or TA0DRAH (TA0DRBH). At the same

time, the set value in the temporary buffer is stored into the double buffer or TA0DRAL

(TA0DRBL). (This structure is designed to enable the set values of the lower-level register and the

higher-level register simultaneously.) Therefore, when setting data to TA0DRA (TA0DRB), be sure

to write the data into TA0DRAL and TA0DRAH (TA0DRBL and TA0DRBH) in this order.

See Figure 13-1 for the temporary buffer configuration.

(2)

Double buffer

In the TMP89FS60, the double buffer can be used by setting TA0CR<TA0DBF>. Setting

TA0CR<TA0DBF> to "0" disables the double buffer. Setting TA0CR<TA0DBF> to "1" enables the

double buffer.

See Figure 13-1 for the double buffer configuration.

- When the double buffer is enabled

When a write instruction is executed on TA0DRAH (TA0DRBH) during the timer opera-

tion, the set value is first stored into the double buffer, and TA0DRAH/L are not updated

immediately. TA0DRAH/L (TA0DRBH/L) compare the last set values to the counter value.

If a match is detected, an INTTCA0 interrupt request is generated and the double buffer set

value is stored into TA0DRAH/L (TA0DRBH/L). Subsequently, the match detection is exe-

cuted using a new set value.

When a read instruction is executed on TA0DRAH/L (TA0DRBH/L), the double buffer

value (the last set value) is read, not the TA0DRAH/L (TA0DRBH/L) values (the current

effective values).

When a write instruction is executed on TA0DRAH/L (TA0DRBH/L) while the timer is

stopped, the set value is immediately stored into both the double buffer and TA0DRAH/L

(TA0DRBH/L).

- When the double buffer is disabled

When a write instruction is executed on TA0DRAH (TA0DRBH) during the timer opera-

tion, the set value is immediately stored in TA0DRAH/L (TA0DRBH/L). Subsequently, the

match detection is executed using a new set value.

If the values set to TA0DRAH/L (TA0DRBH/L) are smaller than the up counter value, the

up counter overflows and the match detection is executed using a new set value. As a result,

the output pulse width may be longer than the set time. If that is a problem, enable the double

buffer.

When a write instruction is executed on TA0DRAH/L (TA0DRBH/L) while the timer is

stopped, the set value is immediately stored into TA0DRAH/L (TA0DRBH/L).

TMP89FS60 Datasheet(PDF) 175 Page - Toshiba Semiconductor

TMP89FS60 Datasheet(HTML) 175 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL