TMP89FS60 datasheet(176/410 Pages) TOSHIBA

176 / 410 page

Page 162

13. 16-bit Timer Counter (TCA)

13.4 Timer Function

TMP89FS60

RA001

Figure 13-8 PPG Mode Timing Chart

Source clock

Counter

Timer start

(Duty pulse)

n (1 cycle)

(Duty pulse)

s (1 cycle)

Write to TA0DRAL, H

Write to TA0DRBL, H

TA0DRAL, H

Match detection

Write n

Write s

Write m

Write r

Becomes the level set at TA0TFF

when the timer is stopped

Reflected by an

interrupt request

Returns to the level

set at TA0TFF

Counter

clear

INTTCA interrupt request

m+1

TA0DRBL, H

TA0CR<TA0S>

Timer stop

Match detection

Counter

clear

r+1

Match detection

TA0MOD<TA0TFF>

PPG0 pin output

Continuous (TA0CR<TA0MPPG>=”0”)

Double buffer (TA0MOD<TA0DBE>=”1”)

(Duty pulse)

Source clock

Counter

Timer start

n (1 cycle)

Write to TA0DRAL, H

Write to TA0DRBL, H

TA0DRAL, H

Match detection

Write n

Write m

Becomes the level set at TA0TFF

when the timer is stopped

Returns to the level

set at TA0TFF

Counter

clear

INTTCA interrupt request

m+1

TA0DRBL, H

TA0CR<TA0S>

Timer stops

automatically

TA0MOD<TA0TFF>

PPG0 pin output

One-shot (TA0CR<TA0MPPG>=”1”)

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