LMK05028RGCT.B datasheet(30/94 Pages) TI2

30 / 94 page

7.3.3 Reference Inputs (INx_P/N)

The reference inputs (IN0 to IN3) can accept differential or single-ended clocks to synchronize any of the PLL

channels. Each input has programmable input type, termination, and AC-coupled input biasing configurations as

shown in Figure 7-10. Each input buffer drives the reference input mux of both DPLL blocks. The DPLL input

mux can select from any of the reference inputs. Any DPLL can switch between inputs with different frequencies

provided the DPLL can be divided-down to a common frequency by DPLL R dividers (DPLLy_REFx_RDIV). The

reference input paths also drive the various detector blocks for reference input monitoring and validation. The

selected reference of each DPLL input (before the R divider) can be routed through the TCXO/Ref bypass mux

and output muxes, allowing a buffered copy of either DPLL reference input on OUT0 and/or OUT1.

LMK05028

Differential or

Single-Ended*

28 pF

100

100 k

VAC-DIFF

(weak bias)

100 k

28 pF

3.6 k

INx_P

INx_ N

To LVCMOS input

slew rate detector

REF path

*Supports 3.3-V

S-E input swing

Figure 7-10. Reference Input Buffer

Table 7-4 lists the reference input buffer configurations for common clock interface types.

Table 7-4. Reference Input Buffer Modes

REFx_TYPE

INPUT TYPES

INTERNAL SWITCH SETTINGS

INTERNAL TERM.

(S1, S2)(1)

INTERNAL BIAS

(S3)(2)

LVCMOS SLEW RATE

DETECT (S4)(3)

LVDS, CML, LVPECL

(DC-coupled)

OFF

LVDS, CML, LVPECL

(AC-coupled)

OFF

ON (1.3 V)

OFF

LVDS, CML, LVPECL

(AC-coupled, internal 100-Ω)

100 Ω

ON (1.3 V)

OFF

HCSL

(DC-coupled, internal 50-Ω)

50 Ω

OFF

LVCMOS

OFF

(1)

S1, S2: OFF = External termination is assumed.

(2)

S3: OFF = External input bias or DC coupling is assumed.

(3)

S4: OFF = Differential input amplitude detector is used for all input types except LVCMOS.

7.3.4 Clock Input Interfacing and Termination

Figure 7-11 through Figure 7-18 show the recommended input interfacing and termination circuits. Unused clock

inputs can be left floating or pulled down.

LMK05028

SNAS724B – FEBRUARY 2018 – REVISED FEBRUARY 2025

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