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LMK05028RGCT.B Datasheet(PDF) 47 Page - Texas Instruments |
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LMK05028RGCT.B Datasheet(HTML) 47 Page - Texas Instruments |
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47 / 94 page  Output Channel Configuration LMK05028 PLL1 VCO1 ÷P1 DPLL feedback Ref Bypass Mux XO TCXO REF B REF A 0 1 2 ÷OD 20-b 0 1 2 3 ÷OD 20-b OUT7 0 1 2 3 4 5 0 1 2 3 4 5 ÷OD 20-b ÷ODB 11-b OUT1 0 1 2 3 0 1 2 3 OUT6 OUT5 OUT4 0 1 2 3 ÷OD 20-b OUT3 OUT2 OUT0 ÷OD 20-b Clock Bus 0 1 2 3 4 5 PLL2 /4 to /9, /11, /13 VCO2 DPLL feedback 4.8 to 5.4 GHz 5.5 to 6.2 GHz Auto SYNC at POR only /4 to /9, /11, /13 ÷P2 ÷P1 ÷P2 GPIO0/SYNCN (active-low pin) SYNC_SW ÷OD SYNC ÷OD 20-b ÷ODB 11-b Power- down Output Type, Slew Rate Mux Auto Mute, Mute Level 2 2 SYNC SYNC EN (1) OUT[4:7] Bank preferred for PLL1 clocks OUT[0:3] Bank preferred for PLL2 clocks A. SYNC Enable logic: SYNC EN = ((CH[z]_SYNCEN) && (PLL[x]_[y]_CH[zz]_SYNC_BANK)) where [x]: PLL = 1 or 2, [y]: Post-Div = PRI or SEC (÷P1 or P2), [z]: CH = 0, 1, 23, 45, 6, or 7, and [zz]: Bank = 03 or 47. Figure 7-27. Output Clock Distribution 7.3.11 Output Channel Muxes Each of the six output channels has as output mux. Each output mux for OUT2 through OUT7 can individually select between the PLL1 and PLL2 post-divider clocks. Each output mux for OUT0 and OUT1 can individually select between the PLL1 and PLL2 post-divider clocks, the XO clock, or one of the clocks from the TCXO/Ref Bypass Mux. 7.3.11.1 TCXO/Ref Bypass Mux The TCXO/Ref bypass mux can select between the TCXO clock, the selected DPLL1 input (REF A), or the selected DPLL2 input (REF B). The bypass clocks are primarily intended for diagnostic purposes and not optimized for lowest phase noise or jitter. 7.3.12 Output Dividers Each of the six output channels has an output divider after the output mux. OUT2 and OUT3 share an output divider, as do OUT4 and OUT5. OUT0, OUT1, OUT6, and OUT7 have the own output dividers. The output divider is used to generate the final output clock frequency from the source selected by the output mux. www.ti.com LMK05028 SNAS724B – FEBRUARY 2018 – REVISED FEBRUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 47 Product Folder Links: LMK05028 |
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