LMK05028RGCT.B datasheet(73/94 Pages) TI2

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8.1.2 Power Down (PDN) Pin

The PDN pin (active low) can be used for device power-down and used to initialize the POR sequence. When

PDN is pulled low, the entire device is powered down and the serial interface is disabled. When PDN is pulled

high, the device POR sequence is triggered to begin the device start-up sequence and normal operation as

depicted in Figure 8-1. If the PDN pin is toggled to issue a momentary hard reset, the negative pulse applied to

the PDN pin must be greater than 200 ns to be captured by the internal digital system clock.

Table 8-1. PDN Control

PDN PIN STATE

DEVICE OPERATION

Device is disabled

Normal operation

8.1.3 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains

8.1.3.1 Mixing Supplies

The LMK05028 incorporates flexible power supply architecture. While all VDD core supplies must be powered by

the same 3.3-V rail, the individual output supplies can be powered from separate 1.8-V, 2.5-V or 3.3-V rails. This

can allow all output supplies at 1.8 V to minimize power consumption. This feature can also allow mixed output

driver levels simultaneously, for example, a 2.5-V LVCMOS clock from a 2.5-V rail and other differential clocks

from a 1.8-V rail.

8.1.3.2 Power-On Reset (POR) Circuit

The LMK05028 integrates a built-in power-on reset (POR) circuit that holds the device in reset until all of the

following conditions have been met:

• All VDD core supplies have ramped above 2.72 V

• PDN pin has ramped above 1.2 V (VIH)

8.1.3.3 Powering Up From a Single-Supply Rail

As long as all VDD core supplies are driven by the same 3.3-V supply rail that ramp in a monotonic manner from

0 V to 3.135 V, irrespective of the ramp time, then there is no requirement to add a capacitor on the PDN pin

to externally delay the device power-up sequence. As shown in Figure 8-2, the PDN pin can be left floating or

otherwise driven by a system host device to meet the clock sequencing requirements in the system.

0 V

Decision Point 2:

VDD_PLLx/VDD_INx/

VDD_DIG / VDD_XO /

VDD_7&;2 • 2.72 V

3.135 V

Decision Point 1:

3'1 •

1.2 V

VDD_PLLx, VDD_INx,

VDD_DIG, VDD_XO,

VDD_TCXO, PDN

200 k

VDD_DIG

PDN

Figure 8-2. Recommendation for Power Up From a Single-Supply Rail

8.1.3.4 Power Up From Split-Supply Rails

If some VDD core supplies are driven from different supply rails, TI recommends starting the PLL calibration

after all of the core supplies have settled at 3.135 V. This can be realized by delaying the PDN low-to-high

transition. The PDN input incorporates a 200-kΩ resistor to VDD_DIG and as shown in Figure 8-3, a capacitor

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LMK05028

SNAS724B – FEBRUARY 2018 – REVISED FEBRUARY 2025

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