LMK05028RGCT.B datasheet(59/94 Pages) TI2

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7.4.3 PLL Start-Up Sequence

Figure 7-40 shows the general sequence for PLL start-up after device configuration. This sequence is also

applicable after a device soft-reset or individual PLL soft-reset. To provide proper VCO calibration, the external

XO clock must be stable in amplitude and frequency prior to the start of VCO calibration; otherwise, the VCO

calibration can fail and prevent start-up of the PLL and the output clocks.

TCXO-DPLL Locked

(Free-run from

TCXO)

VCO Calibration

See DPLL Modes and

Input Selection

Flowcharts

Outputs locked to XO frequency.

Outputs with DPLL auto-mute disabled are un-muted.

Outputs are auto-SYNCed if enabled.

XO Detected

Input Monitoring (fastest to slowest detector):

1. Missing and/or Early clock detector

2. Amplitude or Slew rate detector

3. Frequency (ppm) detector

4. After enabled detectors are valid, validation timer

starts and must finish for input to be qualified.

TCXO Detected

Outputs locked to TCXO/OCXO frequency.

Skip step if 2-loop REF-DPLL mode is

configured (TCXO-DPLL is not used).

REF-DPLL

Lock Acquisition

APLL Locked

(Free-run from XO)

Ref. Input

Validation

REF-DPLL

Locked

Fastlock bandwidth temporarily asserted

during lock acquisition, if enabled.

Outputs locked to selected input clock frequency.

Outputs with DPLL auto-mute enabled are un-muted.

The configured DPLL loop bandwidth is asserted.

DPLL frequency- and phase-lock detectors are monitored.

If Zero-Delay Mode (ZDM) is enabled, output will have

deterministic input-to-output phase relationship.

TCXO-DPLL

DCO Mode control

available

2-loop TCXO-

DPLL mode

REF-DPLL modes

PLL Initialization Sequence

REF-DPLL

DCO Mode control

available (ZDM

must be disabled)

Valid Input Selected

CAL Done

Device Configured / Reset.

See Device POR

Configuration Flowchart

Figure 7-40. PLL Start-Up Sequence

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LMK05028

SNAS724B – FEBRUARY 2018 – REVISED FEBRUARY 2025

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