LMK05028RGCT.B datasheet(46/94 Pages) TI2

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In 2-loop TCXO-DPLL mode, the REF-DPLL is not used and the TCXO-DPLL loop filter output controls the APLL

SDM to steer the VCO frequency into lock with the TCXO input.

7.3.9.14 REF-DPLL and TCXO-DPLL Feedback Dividers

The feedback path of each REF-DPLL and TCXO-DPLL has a feedback prescaler (PR) followed by a fractional

FB divider. The prescaler divides the PLL primary post-divider (P1) clock by a programmable value from 2 to 17,

which then clocks the FB divider. The FB divider of each REF-DPLL and TCXO-DPLL includes a 30-b integer

portion (INT), 40-b numerator portion (NUM), and 40-b denominator portion (DEN). The total FB divider value is:

FB = INT + NUM / DEN. All DPLL feedback dividers are programmable, except for the DENTCXO (fixed, 240). The

FB divider clock must match the TDC rate determined by the TDC input path of the respective DPLL.

The REF-DPLL TDC rate is:

fREF-TDC = fVCO / (P1PLL × PRREF × FBREF)

(14)

The TCXO-DPLL TDC rate is:

fTCXO-TDC = fVCO / (P1PLL × PRTCXO × FBTCXO)

(15)

7.3.10 Output Clock Distribution

The output clock distribution blocks shown in Figure 7-27 includes six output muxes, a TCXO/Ref Bypass mux,

six output dividers, and eight programmable output drivers. The output dividers support output synchronization

(SYNC) to allow phase synchronization between two or more output channels. Also, each output bank (OUT[0:3]

and OUT[4:7]) has separate a zero-delay feedback path to support the zero-delay mode option available on

each DPLL channel.

LMK05028

SNAS724B – FEBRUARY 2018 – REVISED FEBRUARY 2025

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LMK05028RGCT.B Datasheet(PDF) 46 Page - Texas Instruments