LMK05028RGCT.B datasheet(4/94 Pages) TI2

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Table 4-1. Pin Functions (continued)

TYPE(1)

DESCRIPTION

NAME

NO.

VDD_APLL1

Core Supply (3.3 V) for PLL1, PLL2, and Digital Blocks.

Place a nearby 0.1-µF bypass capacitor on each pin.

VDD_APLL2

VDD_DIG

VDDO_0

Output Supply (1.8, 2.5, or 3.3 V) for Clock Outputs 0 to 7.

Place a nearby 0.1-µF bypass capacitor on each pin.

VDDO_1

VDDO_23

VDDO_45

VDDO_6

VDDO_7

CORE BLOCKS

LF1

External Loop Filter Capacitor for APLL1 and APLL2.

Place a nearby 0.1-µF capacitor on each pin.

LF2

CAP_APLL1

External Bypass Capacitors for APLL1, APLL2, and Digital Blocks.

Place a nearby 10-µF bypass capacitor on each pin.

CAP_APLL2

CAP_DIG

INPUT BLOCKS

IN0_P

DPLL Reference Clock Inputs 0 to 3.

Each input pair can accept a differential or single-ended clock signal for synchronizing the DPLLs.

Each pair has a programmable input type with internal termination to support AC- or DC-coupled

clocks. A single-ended LVCMOS clock can be applied to the P input with the N input pulled down

to ground. An unused input pair can be left floating. LVCMOS input mode is recommended for input

frequencies less than 5 MHz.

IN0_N

IN1_P

IN1_N

IN2_P

IN2_N

IN3_P

IN3_N

XO_P

XO Input.

This input pair can accept a differential or single-ended clock signal from a low-jitter local oscillator

to lock the APLLs. This input has a programmable input type with internal termination to support

AC- or DC-coupled clocks. A single-ended LVCMOS clock (up to 2.5 V) can be applied to the P

input with the N input pulled down to ground.

XO_N

TCXO_IN

TCXO Input.

This input can accept an AC-coupled sinewave, clipped-sinewave, or single-ended clock signal from

a stable oscillator (TCXO/OCXO) to lock the TCXO-DPLL if used by a DPLL configuration. The

input swing must be less than 1.3 Vpp before AC-coupling to the input pin, which has weak internal

biasing of 0.6 V and no internal termination. Leave pin floating if unused.

OUTPUT BLOCKS

OUT0_P

Clock Outputs 0 to 3 Bank.

Each programmable output driver pair can support AC-LVDS, AC-CML, AC-LVPECL, HCSL, or

1.8/2.5-V LVCMOS clocks (one or two per pair). Unused differential outputs must be terminated if

active or left floating if disabled through registers.

The OUT[0:3] bank requires at least one clock from the PLL2 domain if enabled. This bank is

preferred for PLL2 clocks to minimize output crosstalk.

OUT0_N

OUT1_P

OUT1_N

OUT2_P

OUT2_N

OUT3_P

OUT3_N

LMK05028

SNAS724B – FEBRUARY 2018 – REVISED FEBRUARY 2025

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