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LMK05028RGCT.B Datasheet(PDF) 75 Page - Texas Instruments |
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LMK05028RGCT.B Datasheet(HTML) 75 Page - Texas Instruments |
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75 / 94 page  OUT0_P OUT0_N CONNECT E-PAD TO PCB GROUND LAYERS WITH 7 x 7 VIA PAT TERN. LF2 LF1 CDIG CP LL1 CP LL2 OUT1_P OUT1_N OUT2_P OUT2_N OUT3_P OUT3_N OUT4_P OUT4_N OUT5_P OUT5_N OUT6_P OUT6_N OUT7_P OUT7_N IN0_P IN0_N IN1_P IN1_N IN2_P IN2_N IN3_P IN3_N XO_P XO_N TCXO_IN INSEL0_0 INSEL0_1 INSEL1_0 INSEL1_1 HW_SW_CTRL GPIO0 GPIO6 GPIO5 GPIO3 GPIO4 STATUS 1 STATUS 0 PDN 0.1µF C15 0.1µF C16 0.1µF C17 0.1µF C18 0.1µF C19 0.1µF C20 0.1µF C21 0.1µF C22 0.1µF C23 VDDO0 VDDO1 VDDO23 VDDO45 VDDO6 VDDO7 0.1µF C25 0.1µF C26 0.1µF C27 0.1µF C28 0.1µF C29 0.1µF C30 VDDXO VDDDIG VDDPLL1 VDDPLL2 LMK05028 VDD 4 E/C 1 GND 2 OUT 3 Y1 0.1µF C39 FB6 100 R22 10µF C32 10µF C33 10µF C34 Place C near pins 49.9 R18 CAP_APLL2 38 CAP_APLL1 48 CAP_DIG 7 GP IO0 45 GP IO1 24 GP IO2 60 GP IO3 40 GP IO4 41 GP IO5 12 GP IO6 13 HW_S W_CTRL 64 IN0_N 2 IN0_P 1 IN1_N 15 IN1_P 14 IN2_N 11 IN2_P 10 IN3_N 6 IN3_P 5 INSEL0_0 20 INSEL0_1 17 INSEL1_0 28 INSEL1_1 29 LF2 39 LF1 47 OUT0_N 23 OUT0_P 22 OUT1_N 26 OUT1_P 27 OUT2_N 32 OUT2_P 31 OUT3_N 33 OUT3_P 34 OUT4_N 52 OUT4_P 51 OUT5_N 53 OUT5_P 54 OUT6_N 58 OUT6_P 57 OUT7_N 61 OUT7_P 62 PAD 65 PDN 46 SCL 36 SDA 35 S TAT US0 55 S TAT US1 56 TCXO_IN 18 VDDO_0 21 VDDO_1 25 VDDO_23 30 VDDO_45 50 VDDO_6 59 VDDO_7 63 VDD_APLL2 37 VDD_APLL1 49 VDD_DIG 8 VDD_IN0 3 VDD_IN1 16 VDD_IN2 9 VDD_IN3 4 VDD_TCXO 19 VDD_XO 42 XO_N 44 XO_P 43 U1 LMK05028RGC 10µF C40 0.1µF C35 0.1µF C31 0.1µF C24 3.3V_LDO 0.1µF C41 0.1µF C38 Place C+R near XO_P (or TCXO_IN) pin 220 ohm FB1 10µF C4 0.1µF C1 VDDIN 3.3V 220 ohm FB2 10µF C5 0.1µF C2 VDDXO 3.3V 1µF C3 3.3V VDDDIG 220 ohm FB3 10µF C11 0.1µF C6 VDDP LL1 3.3V 220 ohm FB4 10µF C12 0.1µF C7 VDDP LL2 3.3V 220 ohm FB5 10µF C13 0.1µF C8 VDDOx 1.8V/2.5V/3.3V GPIO0 GPIO6 GPIO5 GPIO3 GPIO1(SCS ) GPIO2(SDO) GPIO4 10k R2 10k R3 10k R4 10k R5 10k R6 10k R7 10k R8 10k R12 10k R13 10k R14 10k R15 10k R16 10k R17 DNP DNP DNP DNP DNP DNP PDN C14 DNP SDA(SDI) SCL(SCK) 1.5V-3.3V 4.7k R9 4.7k R10 10k R11 HW_SW_CTRL TP2 TP1 50R 50R OUT0_P OUT0_N Vbia s AC-DIFF RECEIVER 0.1µF C36 0.1µF C37 IN0_P IN0_N 0.1µF C10 0.1µF C9 DIFF DRIVER POWER FILTERING CLOCK INPUT EXAMPLES CLOCK OUTPUT EXAMPLES LOGIC I/O PINS CONNECT LOGIC I/O P INS TO HOST MCU/FPGA AS NEEDED. LOGIC I/O DEFS. FOR EEPROM START-UP MODE: I2C MODE -- HW_SW_CTRL = 0 - SDA, SCL = I2C DATA, I2C CLK - GPIO0 = OUTPUT SYNC (Active Low) - GPIO[2:1] = I2C ADDR LSB SELECT (00,01,10,11b) - GPIO[4:3] = DP LL1 DCO FDEC:FINC - GPIO[6:5] = DP LL2 DCO FDEC:FINC (or STAT US OUT) SPI MODE -- HW_SW_CTRL = S TAT US[1:0] = FLOAT OR 0.8-V EXTERNAL BIAS (Rpu=10k, Rpd=3.3k) - SDA, SCL = S PI DATA IN (SDI), SPI CLK - GPIO1 = S PI SCS - GPIO2 = S PI DATA OUT (SDO) - GPIO[0,3-6] = S a me a s for HW_SW_CTRL = 0 VDDIN VDDIN VDDIN VDDIN VDDIN Place C near pins XO_P (TCXO_IN) 3.3-V LVCMOS OSC EXAMPLE (XO, TCXO) GPIO1(SCS ) GPIO2(SDO) SDA(SDI) SCL(SCK) IN1_P LVCMOS DRIVER R1 22 IN1_N 50R 50R OUT1_P OUT1_N HCSL RECEIVER 0 R19 0 R20 OUT7_P LVCMOS RECEIVER 0 R21 XO_N AC-DIFF HCSL LVCMOS INT. TERM LVCMOS AC-DIFF Ipu/pd Ipu Ibia s Ipu Ibia s Ipu/pd IN (Hi-Z) INTERNAL INP UT DEFAULT STAT ES: - Ibia s = BIASED INTERNALLY - Ipu = P ULLUP (whe n P DN = 0) - Ipd = P ULLDOWN (whe n P DN = 0) - Ipu/pd = BIASED TO 0.8 V (whe n P DN = 0) EXT. TERM IN+ IN- IN+ IN- OUT+ OUT- OUT 1.8 V, 2.5 V 1.8 V to 3.3 V Figure 8-4. LMK05028 Reference Schematic Example www.ti.com LMK05028 SNAS724B – FEBRUARY 2018 – REVISED FEBRUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 75 Product Folder Links: LMK05028 |
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