LMK05028RGCT.B datasheet(33/94 Pages) TI2

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The currently selected reference input for each DPLL can be read through the status pin or register.

7.3.5.1 Automatic Input Selection

There are two automatic input selection modes that can be set by a register: Auto Revertive and Auto Non-

Revertive.

• Auto Revertive: In this mode, the DPLL automatically selects the valid input with the highest configured

priority. If a clock with higher priority becomes valid, the DPLL automatically switches over to that clock

immediately.

• Auto Non-Revertive: In this mode, the DPLL automatically selects the highest priority input that is valid. If a

higher priority input because valid, the DPLL does not switch-over until the currently selected input becomes

invalid.

7.3.5.2 Manual Input Selection

There are two manual input selection modes that can be set by a register: Manual with Auto-Fallback and

Manual with Auto-Holdover. In either manual mode, the input selection can be done through register control

(Table 7-5) or hardware pin control (Table 7-6).

• Manual with Auto-Fallback: In this mode, the manually selected reference is the active reference until the

reference becomes invalid. If the reference becomes invalid, the DPLL does automatically fallback to the

highest priority input that is valid or qualified. If no prioritized inputs are valid, the DPLL enters holdover mode

(if tuning word history is valid) or free-run mode. The DPLL exits holdover mode when the selected input

becomes valid.

• Manual with Auto-Holdover: In this mode, the manually selected reference is the active reference until the

reference becomes invalid. If the reference becomes invalid, the DPLL automatically enters holdover mode

(if tuning word history is valid) or free-run mode. The DPLL exits holdover mode when the selected input

becomes valid.

Table 7-5. Manual Input Selection by Register Bits

DPLLx_REF_MAN_REG_SEL[2:0]

BITS

DPLLx_REF_MAN_SEL BIT

SELECTED INPUT

000b

IN0

001b

IN1

010b

IN2

011b

IN3

100b

VCO1 Loopback to DPLL2

101b

VCO2 Loopback to DPLL1

Table 7-6. Manual Input Selection by Hardware Pins

INSELx_[1:0] PINS

DPLLx_REF_MAN_SEL BIT

SELECTED INPUT

00b

IN0

01b

IN1

10b

IN2

11b

IN3

The reference input selection flowchart is shown in Figure 7-19.

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LMK05028

SNAS724B – FEBRUARY 2018 – REVISED FEBRUARY 2025

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