LMK05028RGCT.B datasheet(44/94 Pages) TI2

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LF1, LF2

LMK05028

PFD /

Charge Pump

VCO

Programmable

Loop Filter

Figure 7-26. Loop Filter Structure of Each APLL

7.3.9.6 APLL Voltage Controlled Oscillator (VCO)

Each PLL contains fully-integrated LC-based oscillators with very low phase noise. The VCO takes the voltage

from the loop filter and converts this into a frequency. The tuning range of VCO1 is 4.8 to 5.4 GHz, and the

tuning range of VCO2 is 5.5 to 6.2 GHz. The two VCO frequency ranges are spaced apart to cover a wide range

of frequency configurations and to help minimize cross-coupling between the two PLL domains.

7.3.9.6.1 VCO Calibration

Each PLL's VCO must be calibrated to ensure that the PLL can achieve lock and deliver optimal phase noise

performance. Fundamentally, the VCO calibration establishes an optimal operating point within the tuning range

of the VCO. The VCO calibration is executed automatically during initial PLL start-up after device power-on, hard

reset, or soft reset once the XO input is detected by its input monitor. To ensure proper VCO calibration, it is

critical for the XO clock to be stable in amplitude and frequency prior to the start of VCO calibration; otherwise,

the VCO calibration can fail and prevent start-up of the PLL and its output clocks. Prior to VCO calibration and

APLL lock, the output drivers are typically held in the mute state (configurable per output) to prevent spurious

output clocks.

To trigger VCO calibration for one PLL channel without affecting the other channel, this can be achieved through

host programming by either entering/exiting PLL power-down (PLLx_PDN register bit) or by asserting a PLL

soft-reset (SWRxPLL register bit).

7.3.9.7 APLL VCO Post-Dividers (P1, P2)

The APLL has a primary (P1) and secondary (P2) VCO post-divider for flexible clock frequency planning. All

post-divider supports divide by 4 to 9, 11, or 13. The post-divider clocks for both PLLs are distributed to all output

channel muxes for selection. The primary (P1) post-divider output is also fed back to the FB divider paths of the

REF-DPLL and TCXO-DPLL to close the loops.

After the P1 divider and DPLL fractional FB divider values have been determined for closed-loop operation, the

P1 divider value must not be modified dynamically because the values affects the FB divider clock frequency

to the TDC of the DPLL. If the P1 divider must be changed, re-compute the DPLL FB divider values. Also,

changing any PLL post-divider value requires a PLL soft-reset (or device soft-reset) to reset the divider for

proper operation.

7.3.9.8 APLL Fractional N Divider (N) With SDM

The APLL fractional N divider includes a 9-b integer portion (INT), 40-b numerator portion (NUM), a fixed

40-b denominator portion (DEN), and sigma-delta modulator. The INT and NUM are programmable, while the

denominator is fixed to 240 for highest frequency resolution (step size) on the output. The total N divider value is:

N = INT + NUM / DEN.

LMK05028

SNAS724B – FEBRUARY 2018 – REVISED FEBRUARY 2025

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