LMK05028RGCT.B datasheet(5/94 Pages) TI2

5 / 94 page

Table 4-1. Pin Functions (continued)

TYPE(1)

DESCRIPTION

NAME

NO.

OUT4_P

Clock Outputs 4 to 7 Bank.

Each programmable output driver pair can support AC-LVDS, AC-CML, AC-LVPECL, HCSL, or

1.8/2.5-V LVCMOS clocks (one or two per pair). Unused differential outputs must be terminated if

active or left floating if disabled through registers.

The OUT[4:7] bank requires at least one clock from the PLL1 domain. This bank is preferred for

PLL1 clocks to minimize output crosstalk.

OUT4_N

OUT5_P

OUT5_N

OUT6_P

OUT6_N

OUT7_P

OUT7_N

LOGIC CONTROL / STATUS (2) (3)

HW_SW_CTRL

Device Start-Up Mode Select (3-level, 1.8-V compatible).

This input selects the device start-up mode that determines the memory page used to initialize

the registers, serial interface, and logic pin functions. The input level is sampled only at device

power-on reset (POR).

See Table 4-2 for start-up mode descriptions and logic pin functions.

PDN

Device Power-Down (active low).

When PDN is pulled low, the device is in hard reset and all blocks including the serial interface are

powered down. When PDN is pulled high, the device is started according to device mode selected

by HW_SW_CTRL and begins normal operation with all internal circuits reset to their initial state.

SDA/SDI

I/O

I2C Serial Data I/O (SDA) or SPI Serial Data Input (SDI). See Table 4-2.

The default 7-bit I2C address is 11000xxb, where the MSB bits (11000b) are initialized from on-chip

EEPROM and the LSB bits (xxb) are determined by the logic input pins. When HW_SW_CTRL is 0,

the LSBs are determined by the GPIO[2:1] input levels during POR. When HW_SW_CTRL is 1, the

LSBs are fixed to 00b.

SCL/SCK

I2C Serial Clock Input (SCL) or SPI Serial Clock Input (SCK). See Table 4-2.

GPIO0/SYNCN

Multifunction Inputs or Outputs.

See Table 4-2.

GPIO1/SCS

GPIO2/SDO

I/O

GPIO3/FINC1

GPIO4/FDEC1

GPIO5/FINC2

I/O

GPIO6/FDEC2

I/O

STATUS1

I/O

Status Outputs [1:0].

Each output has programmable status signal selection, driver type (3.3-V LVCMOS or open-drain),

and status polarity. Open-drain requires an external pullup resistor. Leave pin floating if unused.

STATUS0

I/O

INSEL0_1

Manual Reference Input Selection for DPLL1.

INSEL0_[1:0] = 00b (IN0), 01b (IN1), 10b (IN2), or 11b (IN3). Leave pin floating if unused.

INSEL0_0

INSEL1_1

Manual Reference Input Selection for DPLL2.

INSEL1_[1:0] = 00b (IN0), 01b (IN1), 10b (IN2), or 11b (IN3). Leave pin floating if unused.

INSEL1_0

(1)

G = Ground, P = Power, I = Input, O = Output, I/O = Input or Output, A = Analog.

(2)

Internal resistors: PDN pin has 200-kΩ pullup to VDD. Each HW_SW_CTRL, GPIO, and STATUS pin has a 150-kΩ bias to VIM

(approximately 0.8 V) when PDN = 0 or 400-kΩ pulldown when PDN = 1. Each INSEL pin has an 85-kΩ pullup to 1.8 V when PDN = 0

or 400-kΩ pulldown when PDN = 1.

(3)

Unless otherwise noted: Logic inputs are 2-level, 1.8-V compatible inputs. Logic outputs are 3.3-V LVCMOS levels.

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LMK05028

SNAS724B – FEBRUARY 2018 – REVISED FEBRUARY 2025

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