LMK05028RGCT.B datasheet(76/94 Pages) TI2

76 / 94 page

8.2.1 Design Requirements

In a typical application, the following design requirements or parameters must be considered to implement the

overall clock solution:

1. Device initial configuration: Host programmed (MCU or FPGA) or factory pre-programmed.

2. Device start-up mode and serial interface. Typically, this is EEPROM + I2C or SPI mode.

3. XO frequency, signal type, and phase noise or jitter

4. TCXO frequency and stability if any of the following is required:

• Standard-compliant frequency stability (such as SyncE, SONET/SDH, IEEE 1588)

• Lowest possible close-in phase noise at offsets ≤ 100 Hz

• Narrow DPLL bandwidth ≤ 10 Hz

5. For each PLL domain, determine the following:

• Input clocks: frequency, buffer mode, priority, and input selection mode

• Output clocks: frequency, buffer mode

• DPLL loop mode, loop bandwidth, and market segment

• DCO mode or Zero delay

6. Input clock and PLL monitoring options

7. Status outputs and interrupt flag

8. Power supply rails

8.2.2 Detailed Design Procedure

In a typical application, TI recommends the following steps:

1. The LMK05028 GUI in the TICS Pro programming software has a step-by-step design flow to enter the

design parameters, calculate the frequency plan for each PLL domain, and generate the register settings for

the desired configuration. The register settings can be exported (in hex format) to enable host programming

or factory pre-programming.

• If using a generic (non-custom) device, a host device can program the register settings through the serial

interface after power-up and issue a soft-reset (by RESET_SW bit) to start the device. The host can

also store the settings to the EEPROM to allow self-startup with these register settings on subsequent

power-on reset cycles.

• Alternatively, a LMK05028 setup file for TICS Pro (.tcs) can be sent to TI to request custom factory

pre-programmed devices.

2. Tie the HW_SW_CTRL pin to ground to select EEPROM+I2C mode, or bias the pin to VIM through the

weak internal resistors or external resistors to select EEPROM+SPI mode. Determine the logic I/O pin

assignments for control and status functions. See Device Start-Up Modes.

• Connect I2C/SPI and logic I/O pins (1.8-V compatible levels) to the host device pins with the proper I/O

direction and voltage levels.

3. Select a XO frequency by following Oscillator Input (XO_P/N).

• Choose a XO with target phase jitter performance < 300 fs RMS (12 kHz to 20 MHz).

• For a 3.3-V LVCMOS driver, follow the OSC clock interface example in Figure 8-4. Power the OSC from a

low-noise LDO regulator or optimize the supply filtering to avoid supply-induced jitter on the XO clock.

• TICS Pro: Configure the XO input buffer mode to match the XO driver interface requirements. See Table

7-3.

4. If a TCXO/OCXO is needed, select the frequency by following TCXO/OCXO Input (TCXO_IN).

• Choose a TCXO/OCXO that meets the frequency stability and accuracy requirements required for the

output clocks during free-run or holdover.

• For a 3.3-V LVCMOS driver, follow the OSC clock interface example in Figure 8-4.

• A (clipped) sinewave TCXO/OCXO with less than 1.3-Vpp swing can be simply AC-coupled to the input

pin.

• TICS Pro: The TCXO/OCXO input buffer is enabled when either PLL channel uses the TCXO-DPLL.

LMK05028

SNAS724B – FEBRUARY 2018 – REVISED FEBRUARY 2025

www.ti.com

Submit Document Feedback

Product Folder Links: LMK05028

LMK05028RGCT.B Datasheet(PDF) 76 Page - Texas Instruments

LMK05028RGCT.B Datasheet(HTML) 76 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94

Datasheet Download

Link URL