LMK05028RGCT.B datasheet(40/94 Pages) TI2

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7.3.8.6 Status Outputs

STATUS[1:0] and GPIO[6:5] pins can be configured to output various status signals and interrupt flag for

device diagnostic and debug purposes. The status signal, output driver type, and output polarity settings are

programmable. The status output signals available at these pins for each device block monitored are listed in

Equation 10. When the status signal is asserted, the status output is active high (assuming the status polarity is

not set to active low).

Table 7-7. Status Pin Signals Available per Device Block

DEVICE BLOCK MONITORED

STATUS SIGNAL (ACTIVE HIGH)

XO Input Loss of Signal (LOS)

TCXO

TCXO Input Loss of Signal (LOS)

APLL1, APLL2

APLLx Lock Detected ( LOL)

PLLx VCO Calibration Active

APLLx N Divider, div-by-2

EEPROM

EEPROM Active

All Inputs and PLLs

Interrupt (INTR)

REF0 to REF3 (IN0 to IN3)

REFx Monitor Divider Output, div-by-2

REFx Amplitude Monitor Fault

REFx Frequency Monitor Fault

REFx Missing or Early Pulse Monitor Fault

REFx Validation Timer Active

REFx Phase Validation Monitor Fault

DPLL1, DPLL2

DPLLx R Divider, div-by-2

DPLLx REF N Divider, div-by-2

DPLL TCXO M Divider, div-by-2

DPLLx TCXO N Divider, div-by-2

DPLLx REFn Selected

DPLLx Holdover Active

DPLLx Reference Switchover Event

DPLLx Tuning History Update

DPLLx Loss of Lock (LOFL)

7.3.8.7 Interrupt

Any of the four status pins can be configured as a device interrupt output pin. The interrupt configuration is

set through registers. When the interrupt is enabled, the interrupt flag can be triggered from any combination

of interrupt status indicators, including LOS for the XO, TCXO, and DPLL-selected inputs, LOL for each DPLL

and APLL, and holdover and switchover events for each DPLL. Any status indicator can be masked so the

indicator does not trigger the interrupt pin. Any unmasked status indicator can have the polarity inverted before

the indicator is combined at the interrupt AND/ OR gate and output to the status pin.

When the interrupt output is enabled and an interrupt flag is asserted by one or more fault conditions, the host

device can read the sticky status registers to identify which flags were set, resolve any fault conditions in the

system, and clear the flag by writing 0 to clear the sticky bits that were set.

LMK05028

SNAS724B – FEBRUARY 2018 – REVISED FEBRUARY 2025

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