MC68HC705P9CS datasheet(132/160 Pages) FREESCALE

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Analog-to-Digital Converter (ADC)

Technical Data

MC68HC705P9 — Rev. 4.0

132

Analog-to-Digital Converter (ADC)

MOTOROLA

11.4.1.2 PC6/AN0–PC3/AN3

The multiplexer can select one of four external analog input channels

(AN0, AN1, AN2, or AN3) for sampling. The conversion takes 32 cycles.

The first 12 cycles sample the voltage on the selected input pin by

charging an internal capacitor. In the last 20 cycles, a comparator

successively compares the output of an internal D/A converter to the

sampled analog input. Control logic changes the D/A converter input one

bit at a time, starting with the MSB, until the D/A converter output

matches the sampled analog input. The conversion is monotonic and

has no missing codes. At the end of the conversion, the conversion

complete flag (CCF) becomes set, and the CPU takes two cycles to

move the result to the ADC data register.

NOTE:

To prevent excess power dissipation, do not simultaneously use an I/O

port pin as a digital input and an analog input.

While the ADC is on, the selected analog input reads as logic zero. The

port C pins that are not selected read normally.

An analog input voltage equal to V

RH converts to digital $FF; an input

voltage greater than V

RH converts to $FF with no overflow. An analog

input voltage equal to V

SS converts to digital $00. For ratiometric

conversion, the source of each analog input should use V

RH as the

supply voltage and be referenced to V

SS.

The clock frequency must be equal to or greater than 1 þMHz. If the

internal clock frequency is less than 1þMHz, the internal RC oscillator

(nominally 1.5 MHz) must be used for the ADC conversion clock. Make

this selection by setting the ADRC bit to logic one in the ADC status and

control register.

11.5 Interrupts

The ADC cannot generate interrupt requests.

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