CP3SP33SMSSLASHNOPB datasheet(166/407 Pages) TI1

166 / 407 page

CP3SP33

SNOSCW5 – MAY 2013

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VSTATUS

The VSTATUS field returns the data in the register addressed by the VCTRL register.

21.3.27 USB Suspend Control Register (PTCI_SUSPCTRL)

The PTCI_SUSPCTRL register is an 8-bit, write-only register which provides an interface for forcing the

USB transceiver and OTG signals into Suspend mode. At reset, this register is cleared to 00h.

Reserved

SUSPOTG_CTRL

SUSP_CTRL

FORCE_SUSP

FORCE_SUSPOTG

The Force Suspend OTG bit forces the USB OTG signals into Suspend mode,

when selected by the SUSPOTG_CTRL bit.

0 – Normal operation.

1 – Suspend mode.

FORCE_SUSP

The Force Suspend bit forces the USB transceiver into Suspend mode, when

selected by the SUSP_CTRL bit.

0 – Normal operation.

1 – Suspend mode

SUSP_CTRL

The Suspend Control bit selects whether the USB logic or the FORCE_SUSP bit

controls Suspend mode for the USB transceiver.

0 – USB logic.

1 – FORCE_SUSP bit.

SUSPOTG_CTRL

The Suspend OTG bit selects whether the USB logic or the FORCE_SUSPOTG

bit controls Suspend mode for the USB OTG signals.

0 – USB logic.

1 – FORCE_SUSPOTG bit.

22 Dual CAN Interfaces

Each CAN interface contains a Full CAN class, CAN (Controller Area Network) serial bus interface for

low/high speed applications. It supports reception and transmission of extended frames with a 29-bit

identifier, standard frames with an 11-bit identifier, applications that require high speed (up to 1 MBit/s),

and a low-speed CAN interface with CAN master capability. Data transfer between the CAN bus and the

CPU is handled by 15 message buffers per interface, which can be individually configured as receive or

transmit buffers. Every message buffer includes a status/control register which provides information about

its current status and capabilities to configure the buffer. All message buffers are able to assert an

interrupt on the reception of a valid frame or the successful transmission of a frame. In addition, an

interrupt can be generated on bus errors.

An incoming message is only accepted if the message identifier passes one of two acceptance filtering

masks. The filtering mask can be configured to receive a single message ID for each buffer or a group of

IDs for each receive buffer. One of the buffers uses a separate message filtering procedure. This provides

the capability to establish a BASIC-CAN path. Remote transmission requests can be processed

automatically by automatic reconfiguration to a receiver after transmission or by automated transmit

scheduling upon reception. A priority decoder allows any buffer to have one of 16 transmit priorities

including the highest or lowest absolute priority, for a total of 240 different transmit priorities.

A decided bit time counter (16-bit wide) is provided to support real time applications. The contents of this

counter are captured into the message buffer RAM on reception or transmission. The counter can be

synchronized through the CAN network. This synchronization feature allows a reset of the counter after

the reception or transmission of a message in buffer 0.

166

Dual CAN Interfaces

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