CP3SP33SMSSLASHNOPB datasheet(167/407 Pages) TI1

167 / 407 page

CP3SP33

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SNOSCW5 – MAY 2013

The CAN modules are fast APB bus peripherals which allow single-cycle read/write access. The CPU

controls the CAN modules by programming the registers in the CAN register blocks. This includes

initialization of the CAN baud rate, logic level of the CAN pins, and enable/disable of the CAN modules. A

set of diagnostic features, such as loopback, listen only, and error identification, support development with

the CAN modules and provide a sophisticated error management tool.

The CAN modules implement the following features:

•

CAN specification 2.0B

–

Standard data and remote frames

–

Extended data and remote frames

–

0 to 8 bytes data length

–

Programmable bit rate up to 1 Mbit/s

•

15 message buffers, each configurable as receive or transmit buffers

–

Message buffers are 16-bit wide RAM mapped to the lower words of a 32-bit wide memory space

–

One buffer may be used as a BASIC-CAN path

•

Remote Frame support

–

Automatic transmission after reception of a Remote Transmission Request (RTR)

–

Auto receive after transmission of a RTR

•

Acceptance filtering

–

Two filtering capabilities: global acceptance mask and individual buffer identifiers

–

One of the buffers uses an independent acceptance filtering procedure

•

Programmable transmit priority

•

Interrupt capability

–

One interrupt vector for all message buffers in each module (receive/transmit/error)

–

Each interrupt source can be enabled/disabled

•

16-bit counter with time stamp capability on successful reception or transmission of a message

•

Power Save capabilities with programmable Wake-Up over the CAN bus (alternate source for the

Multi-Input Wake-Up module)

•

Push-pull capability of the input/output pins

•

Diagnostic functions

–

Error identification

–

Loopback and listen-only features for test and initialization purposes

22.1 Functional Description

As shown in Figure 22-1, the CAN modules consists of three blocks: the CAN core, interface

management, and a RAM containing the message buffers.

There are two dedicated device pins for each CAN interface, CANnTX for the transmit output and

CANnRX for the receive input (n = 0 or 1).

The CAN core implements the basic CAN protocol features such as bit-stuffing, CRC calculation/checking,

and error management. It controls the transceiver logic and creates error signals according to the bus

rules. In addition, it converts the data stream from the CPU (parallel data) to the serial CAN bus data.

The interface management block is divided into the register block and the interface management

processor. The register block provides the CAN interface with control information from the CPU and

provides the CPU with status information from the CAN module. Additionally, it generates the interrupt to

the CPU.

The interface management processor is a state machine executing the CPU’s transmission and reception

commands and controlling the data transfer between several message buffers and the RX/TX shift

registers.

Dual CAN Interfaces

167

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