CP3SP33SMSSLASHNOPB datasheet(162/407 Pages) TI1

162 / 407 page

CP3SP33

SNOSCW5 – MAY 2013

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FLUSHFIFO

The FLUSHFIFO bit is written with 1 to flush the receive FIFO. The FIFO pointer is

reset and the RXPKTRDY bit is cleared. The FLUSHFIFO bit has no effect unless

RXPKTRDY bit is set. If double-buffering is enabled, the FLUSHFIFO bit may need

to be written twice to completely clear the FIFO. The FLUSHFIFO bit is cleared

automatically.

0 – Normal operation.

1 – Flush the transmit FIFO and reset the RXPKTRDY bit.

SENDSTALL

The Send STALL Handshake bit is set by software to issue a STALL handshake.

Software must clear this bit to terminate the STALL condition. This bit is ignored for

Isochronous end-points.

0 – Normal operation.

1 – STALL condition.

SENTSTALL

The Sent STALL Handshake bit is set when a STALL handshake is transmitted.

Software clears this bit to detect the next STALL handshake.

0 – No STALL handshake since the bit was last cleared.

1 – STALL handshake transmitted.

CLRDATATOG

The Clear Data Toggle bit is written with 1 to reset the endpoint data toggle to 0.

0 – Normal operation.

1 – Write 1 to reset endpoint data toggle to 0.

ISO

The Isochronous Transfer bit specifies whether the Bulk/Interrupt or Isochronous

transfer type is used.

0 – Bulk/Interrupt transfer type.

1 – Isochronous transfer type.

AUTOCLEAR

The Automatic Clear bit is set by software to enable a mode in which the

RXPKTRDY bit is automatically cleared when data of the maximum packet size

(value in RXMAXP register) has been unloaded from the receive FIFO. If a packet of

less than the maximum packet size is unloaded, then the RXPKTRDY bit must be

set explicitly by software.

0 – Normal mode.

1 – Automatically clear RXPKTRDY when maximum packet size packet is unloaded

from the receive FIFO.

Host Mode Format

DATAERROR

CLRDATATOG

RXSTALL

REQPKT

FLUSHFIFO

ERROR

FIFOFULL

RXPKTRDY

NAKTIMEOUT

AUTOCLEAR

AUTOREQ

Reserved

RXPKTRDY

The Receive Packet Ready bit is set when a data packet has been received in the

FIFO. Software should clear this bit when the FIFO is unloaded to detect the next

packet. An interrupt is asserted (if enabled) when this bit is set.

0 – No packet in receive FIFO.

1 – Data packet in FIFO, ready to unload.

FIFOFULL

The FIFO Full bit is set when no more packets can be loaded into the receive FIFO.

0 – Receive FIFO is empty.

1 – Receive FIFO is full.

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