CP3SP33SMSSLASHNOPB datasheet(159/407 Pages) TI1

159 / 407 page

CP3SP33

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SNOSCW5 – MAY 2013

FLUSHFIFO

The FLUSHFIFO bit is written with 1 to flush the transmit FIFO. The FIFO pointer is

reset and the TXPKTRDY bit is cleared. The FLUSHFIFO bit has no effect unless

TXPKTRDY bit is set. If double-buffering is enabled, the FLUSHFIFO bit may need to

be written twice to completely clear the FIFO. The FLUSHFIFO bit is cleared

automatically.

0 – Normal operation.

1 – Flush the transmit FIFO and clear the TXPKTRDY bit.

SENDSTALL

The Send STALL Handshake bit is set to send a STALL handshake in response to an

IN token. Software must clear this bit to terminate the STALL condition. This bit is

ignored when the endpoint is used for isochronous transfers.

0 – Normal operation.

1 – STALL condition.

SENTSTALL

The Sent STALL Handshake bit is set when a STALL handshake is transmitted. Also,

the transmit FIFO is flushed, and the TXPKTRDY bit is cleared. Software clears this

bit to detect the next STALL handshake.

0 – No STALL handshake since the bit was last cleared.

1 – STALL handshake transmitted.

CLRDATATOG

The Clear Data Toggle bit is written with 1 to reset the endpoint data toggle to 0.

0 – Normal operation.

1 – Write 1 to reset endpoint data toggle to 0.

FRCDATATOG

The Force Data Toggle bit is written with 1 to force the endpoint data toggle to switch

and the data packet to be cleared from the FIFO, without regard to whether an ACK

was received. This can be used by Interrupt transmit endpoints that are used to

communicate rate feedback for Isochronous endpoints.

0 – Normal operation.

1 – Write 1 to force endpoint data to toggle.

ISO

The Isochronous Transfer bit specifies whether the Bulk/Interrupt or Isochronous

transfer type is used.

0 – Bulk/Interrupt transfer type.

1 – Isochronous transfer type.

AUTOSET

The Automatic Set bit is set by software to enable a mode in which the TXPKTRDY

bit is automatically set when data of the maximum packet size (value in TXMAXP

size is loaded, then the TXPKTRDY bit must be set explicitly by software. The

TXPKTRDY bit is also automatically set when the first of two packets in the transmit

FIFO has been sent and the second packet is the maximum packet size.

0 – Normal mode.

1 – Automatically set TXPKTRDY when maximum packet size packet is loaded into

the transmit FIFO.

Host Mode Format

NAKTIMEOUT

CLRDATATOG

RXSTALL

Reserved

FLUSHFIFO

ERROR

FIFONOTEMPTY

TXPKTRDY

AUTOSET

Reserved

FRCDATATOG

Reserved

TXPKTRDY

The Transmit Packet Ready bit is set by software after loading a data packet into the

FIFO. The bit is cleared automatically when the data packet has been transmitted. An

interrupt is asserted (if enabled) when this bit is cleared.

0 – No packet in transmit FIFO.

1 – Data packet in FIFO, ready to transmit.

USB Controller

159

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