CP3SP33SMSSLASHNOPB datasheet(161/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

21.3.18 Receive Maximum Packet Size Register (RXMAXP)

The RXMAXP register is a 16-bit, read/write register that specifies the maximum amount of data that can

be transferred through the selected receive endpoint in a single frame. The value is subject to the

constraints placed by the USB Specification on packet sizes for Bulk, Interrupt, and Isochronous transfers.

The value should match the wMaxPacketSize field of the Standard Endpoint Descriptor for the associated

endpoint (see Universal Serial Bus Specification Revision 2.0, Chapter 9). A mismatch could cause

unexpected results. The value written to this register must not exceed the receive FIFO size. If the value

written to this register is less than, or equal to, half the receive FIFO size, two packets can be buffered.

There is a RXMAP register for each receive endpoint (except Endpoint 0). At reset, this register is cleared

to 0000h.

11M M10

Reserved

MAXSIZE

MAXSIZE The Maximum Packet Size field specifies (in bytes) the maximum payload received in a

single transaction.

21.3.19 Receive Control and Status Register (RXCSR)

The RXCSR register is a 16-bit, read/write register that provides control and status bits for the associated

endpoint (except Endpoint 0). It has different formats in Peripheral and Host modes. After reset, this

Peripheral Mode Format

CLRDATATOG

SENTSTALL

SENDSTALL

FLUSHFIFO

DATAERROR

OVERRUN

FIFOFULL

RXPKTRDY

AUTOCLEAR

ISO

Reserved

RXPKTRDY

The Receive Packet Ready bit is set when a data packet is received. Software

should clear this bit when the packet is unloaded from the receive FIFO to detect the

next packet. An interrupt is asserted (if enabled) when this bit is set.

0 – No packet in receive FIFO.

1 – Data packet in FIFO, ready to unload.

FIFOFULL

The FIFO Full bit indicates that no more packets can be loaded into the receive

FIFO.

0 – Receive FIFO is not full.

1 – Receive FIFO is full.

OVERRUN

The Overrun bit is set when an OUT packet cannot be loaded into the receive FIFO.

Software clears the OVERRUN bit to detect the next overrun event. This bit is only

valid for Isochronous endpoints.

0 – No overrun event detected since the bit was last cleared.

1 – Overrun event detected.

DATAERROR

The Data Error bit is set when the RXPKTRDY bit is set and the data packet has a

CRC or bit-stuffing error. Software clears this bit to detect the next data error. This

bit is only valid for Isochronous endpoints.

0 – No data error since the bit was last cleared.

1 – Data error detected.

USB Controller

161

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