CP3SP33SMSSLASHNOPB datasheet(157/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

RXSTALL

The Receive STALL handshake bit is set when a STALL handshake is received.

Software clears this bit to detect the next STALL handshake.

0 – No STALL handshake since the bit was last cleared.

1 – STALL handshake received.

SETUPPKT

The Setup Packet bit is set by software at the same time the TXPKTRDY bit is set, to

select a SETUP token instead of an OUT token for the transaction.

0 – OUT token selected.

1 – SETUP token selected

ERROR

The Error bit is set when three attempts have been made to perform a transaction

with no response from the peripheral. An interrupt is asserted when this bit is set.

Software clears this bit to detect the next error event.

0 – No error event detected since the bit was last cleared.

1 – Error event detected.

REQPKT

The Request Packet bit is written with 1 to request an IN transaction. The REQPKT

bit is cleared when the RXPKTRDY bit is set.

0 – No request asserted.

1 – Request for an IN transaction asserted.

STATUSPKT

The Status Packet bit is set by software at the same time as the TXPKTRDY or

REQPKT bit is set, to perform a Status Stage transaction. Setting this bit ensures that

the data toggle is set to 1 so that a DATA1 packet is used for the Status Stage

transaction.

0 – Normal operation.

1 – Status Stage transaction selected.

NAKTIMEOUT

The NAK Timeout bit is set when Endpoint 0 is halted following the receipt of NAK

responses for longer than the time set by the NAKLIMIT0 register. Software must

clear this bit to allow the endpoint to continue.

0 – Normal operation.

1 – Endpoint 0 halted.

FLUSHFIFO

The FLUSHFIFO bit is written with 1 to flush the Endpoint 0 FIFO. The FIFO pointer

is reset and the TXPKTRDY/RXPKTRDY bit is cleared. The FLUSHFIFO bit has no

effect unless TXPKTRDY/RXPKTRDY bit is set.

0 – Normal operation.

1 – Flush the Endpoint 0 FIFO and clear the TXPKTRDY/RXPKTRDY bit.

21.3.14 Endpoint 0 Count Register (COUNT0)

The COUNT0 register is an 8-bit, read-only register that indicates the current number of received data

bytes in the Endpoint 0 FIFO. The value changes as the contents of the FIFO change, and it is only valid

while the CSR0.RXPKTRDY bit is set. At reset, this register is cleared to 00h.

Reserved

COUNT

The Count field indicates how many valid bytes are in the Endpoint 0 receive FIFO.

21.3.15 Endpoint 0 NAK Limit Register (NAKLIMIT0)

The NAKLIMIT0 register is an 8-bit, read/write register that specifies the number of frames after which an

Endpoint 0 timeout occurs in Host mode when receiving a stream of NAK responses. (Equivalent settings

for other endpoints can be made through their TXINTERVAL and RXINTERVAL registers.)

The number of frames is 2m-1, in which m is the value specified in the register. If the host receives NAK

responses from the target for more frames than the number represented by the limit set in this register,

the endpoint will be halted. At reset, this register is cleared to 00h.

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