CP3SP33SMSSLASHNOPB datasheet(155/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

SESSION

The Session bit is set or cleared by software to start or end a session, when operating

as an A device. As a B device, this bit is controlled by hardware to indicate when a

session starts and ends. It is also set by software to initiate the Session Request

Protocol, or cleared by software when in Suspend mode to perform a software

disconnect.

0 – Session disabled.

1 – Session enabled.

HOSTREQ

The Host Request bit is set to initiate the Host Negotiation Protocol when Suspend

mode is entered. It is cleared when Host Negotiation is completed. This bit is only valid

as a B device.

0 – No host negotiation.

1 – Initiate host negotiation.

HOSTMODE

The Host Mode bit indicates whether the USB controller is in Host or Peripheral mode.

This is a read-only bit.

0 – Peripheral mode.

1 – Host mode.

VBUS

The VBUS field indicates the current VBUS level. This is a read-only field.

00 – Below SessionEnd.

01 – Above SessionEnd, below AValid.

10 – Above AValid, below VBusValid.

11 – Above VBusValid.

LSDEV

The Low-Speed Device bit indicates when a low-speed device is detected. Low-speed

mode is not supported. This is a read-only bit.

0 – Low-speed device not detected. 1 – Low-speed device detected.

FSDEV

The Full-Speed Device bit indicates when a full-speed device is detected. This bit is

only valid in Host mode. This is a read-only bit.

0 – Full-speed device not detected.

1 – Full-speed device detected.

BDEVICE

The B Device bit indicates whether the USB controller is operating as an A device or a

B device. This bit is only valid while a session is in progress. This is a read-only bit.

0 – A device.

1 – B device.

21.3.13 Endpoint 0 Control and Status Register (CSR0)

The CSR0 register is a 16-bit, read/write register that provides control and status bits for Endpoint 0. It has

different formats in Peripheral and Host modes. After reset, this register is cleared to 0000h.

Peripheral Mode Format

Reserve

SERVICED

SERVICE

SEND

SETUP

DATA

SENT

FLUSHFIFO

TXPKTRDY

RXPKTRDY

SETUPEND

DRXPKTRDY

STALL

END

STALL

RXPKTRDY

The Receive Packet Ready bit is set when a data packet has been received.

An interrupt is asserted (if enabled) when this bit is set. Software clears the

RXPKTRDY bit by writing 1 to the SERVICEDRXPKTRDY bit.

0 – No data packet received.

1 – Data packet received.

TXPKTRDY

The Transmit Packet Ready bit is set by software after loading a data packet

into the FIFO. The bit is cleared automatically when the data packet has been

transmitted. An interrupt is asserted (if enabled) when this bit is cleared.

0 – No packet in transmit FIFO.

1 – Data packet in FIFO, ready to transmit.

USB Controller

155

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