CP3SP33SMSSLASHNOPB datasheet(152/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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EPnRX

The Endpoint n Receive bit indicates that an interrupt was asserted for Receive Endpoint n (n

= 1 to 3).

0 – No interrupt asserted.

1 – Interrupt asserted.

21.3.5 Interrupt Enable Register for Endpoint 0 and Transmit Endpoints (INTRTXE)

The INTRTXE register is a 16-bit, read/write register that controls whether interrupts are enabled for

Endpoint 0 and the Transmit Endpoints 1, 2, and 3. Bits for endpoints that have not been configured will

always return 0. After reset, this register is initialized to 000Fh.

Reserved

EP3TX

EP2TX

EP1TX

EP0

The Endpoint 0 bit controls whether an interrupt is enabled for Endpoint 0.

0 – No interrupt enabled.

1 – Interrupt enabled.

EPnTX

The Endpoint n Transmit bit controls whether an interrupt is enabled for Transmit Endpoint n

(n = 1 to 3).

0 – No interrupt enabled.

1 – Interrupt enabled.

21.3.6 Interrupt Enable Register for Receive Endpoints (INTRRXE)

The INTRRXE register is a 16-bit, read/write register that controls whether interrupts are enabled for

Receive End-points 1, 2, and 3. After reset, this register is initialized to 000Eh.

Reserved

EP3RX

EP2RX

EP1RX

Reserved

EPnRX

The Endpoint n Receive bit controls whether an interrupt is enabled for Receive Endpoint n

(n = 1 to 3).

0 – No interrupt enabled.

1 – Interrupt enabled.

21.3.7 Interrupt Register for USB Controller (INTRUSB)

The INTRUSB register is an 8-bit, read-only register that indicates which interrupts are currently asserted

for the USB controller. All asserted interrupts are cleared when this register is read. After reset, this

VBUSERROR

SESSREQ

DISCON

CONN

SOF

RESETBABBLE

RESUME

SUSPEND

The Suspend bit indicates that an interrupt was asserted because Suspend signaling

was detected on the bus. This bit is only valid in Peripheral mode.

0 – No interrupt asserted.

1 – Interrupt asserted.

RESUME

The Resume bit indicates that an interrupt was asserted because Resume signaling

was detected while the USB Controller was in Suspend mode.

0 – No interrupt asserted.

1 – Interrupt asserted.

RESETBABBLE

The Reset/Babble bit indicates that an interrupt was asserted because babble was

detected (unexpected bus activity) in Host mode or reset signaling was detected in

Peripheral mode.

0 – No interrupt asserted.

1 – Interrupt asserted.

152

USB Controller

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