CP3SP33SMSSLASHNOPB datasheet(151/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

SOFTCONN

The Soft Connect/Disconnect bit can be used when the USB controller is acting

as a peripheral to switch the USB transceiver between normal mode and non-

driving mode. As a result, it can be used to connect/disconnect the device from

its host without having the change the physical connections, when the device is

acting as a peripheral. After a hardware reset, the SOFTCONN bit is clear. The

USB controller will therefore appear disconnected until the software has set the

SOFTCONN bit. Software can then choose when to set the transceiver into its

normal mode. Systems with a lengthy initialization procedure may use this to

ensure that initialization is complete and the system is ready to perform

enumeration before connecting to the USB. After the SOFTCONN bit has been

set, clearing this bit will put the transceiver into non-driving mode. The USB

controller will then appear to have been disconnected to other devices on the

USB bus. This bit is only valid in Peripheral mode.

0 – USB transceiver is in non-driving mode.

1 – USB transceiver is enabled to drive D+ and D-.

ISOUPDATE

The Isochronous Update bit only affects IN Isochronous endpoints (Endpoint 1).

It is normally used as a method of ensuring a “clean” start-up of an IN

Isochronous pipe. When set, the USB controller will wait for an SOF token from

the time TXPKTRDY is set before sending the packet. If an IN token is received

before an SOF token, then a zero-length data packet will be sent. This bit is only

valid in Peripheral mode.

0 – Normal mode.

1 – Isochronous update mode.

21.3.3 Interrupt Register for Endpoint 0 and Transmit Endpoints (INTRTX)

The INTRTX register is a 16-bit, read-only register that indicates which interrupts are currently asserted for

Endpoint 0 and the Transmit Endpoints 1, 2, and 3. Bits for endpoints that have not been configured will

always return 0. All asserted interrupts are cleared when this register is read. After reset, this register is

cleared to 0000h.

Reserved

EP3TX

EP2TX

EP1TX

EP0

The Endpoint 0 bit indicates that an interrupt was asserted for Endpoint 0.

0 – No interrupt asserted.

1 – Interrupt asserted.

EPnTX

The Endpoint n Transmit bit indicates that an interrupt was asserted for Transmit Endpoint n

(n = 1 to 3).

0 – No interrupt asserted.

1 – Interrupt asserted.

21.3.4 Interrupt Register for Receive Endpoints (INTRRX)

The INTRRX register is a 16-bit, read-only register that indicates which interrupts are currently asserted

for Receive Endpoints 1, 2, and 3. Bits for endpoints that have not been configured will always return 0. All

asserted interrupts are cleared when this register is read. After reset, this register is cleared to 0000h.

Reserved

EP3RX

EP2RX

EP1RX

Reserved

USB Controller

151

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