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CP3SP33SMS/NOPB Datasheet(PDF) 153 Page - Texas Instruments |
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CP3SP33SMS/NOPB Datasheet(HTML) 153 Page - Texas Instruments |
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153 / 407 page  CP3SP33 www.ti.com SNOSCW5 – MAY 2013 SOF The Start of Frame bit indicates that an interrupt was asserted because a new frame started. 0 – No interrupt asserted. 1 – Interrupt asserted. CONN The Connection bit indicates that an interrupt was asserted because a device connection was detected. This bit is only valid in Host mode. 0 – No interrupt asserted. 1 – Interrupt asserted. DISCON The Disconnect bit indicates that an interrupt was asserted because a device disconnect was detected in Host mode or a session ended in Peripheral mode. 0 – No interrupt asserted. 1 – Interrupt asserted. SESSREQ The Session Request bit indicates that an interrupt was asserted because a Session Request signal was detected on the bus. This bit is only valid when the USB controller is an A device. 0 – No interrupt asserted. 1 – Interrupt asserted. VBUSERROR The VBUS Error bit indicates that an interrupt was asserted because VBUS dropped below the VBUS Valid threshold during a session. This bit is only valid when the USB controller is an A device. 0 – No interrupt asserted. 1 – Interrupt asserted. 21.3.8 Interrupt Enable Register for USB Controller (INTRUSBE) The INTRUSBE register is an 8-bit, read/write register that controls which USB controller interrupts are enabled. After reset, this register is initialized to 06h. 7 6 5 4 3 2 1 0 VBUSERROR SESSREQ DISCON CONN SOF RESETBABBLE RESUME SUSPEND SUSPEND The Suspend bit enables an interrupt when Suspend signaling is detected on the bus. This bit is only valid in Peripheral mode. 0 – No interrupt enabled. 1 – Interrupt enabled. RESUME The Resume bit enables an interrupt when Resume signaling is detected while the USB Controller is in Suspend mode. 0 – No interrupt enabled. 1 – Interrupt enabled. RESETBABBLE The Reset/Babble bit enables an interrupt when babble is detected (unexpected bus activity) in Host mode or reset signaling is detected in Peripheral mode. 0 – No interrupt enabled. 1 – Interrupt enabled. SOF The Start of Frame bit enables an interrupt when a new frame starts. 0 – No interrupt enabled. 1 – Interrupt enabled. CONN The Connection bit enables an interrupt when a device connection is detected. This bit is only valid in Host mode. 0 – No interrupt enabled. 1 – Interrupt enabled. Copyright © 2013, Texas Instruments Incorporated USB Controller 153 Submit Documentation Feedback Product Folder Links :CP3SP33 |
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